STM32L4R9ZIT6STR datasheet(44/307 Pages) STMICROELECTRONICS

44 / 307 page

Functional overview

STM32L4R5xx, STM32L4R7xx and STM32L4R9xx

44/307

DS12023 Rev 5

3.18

Interrupts and events

3.18.1

Nested vectored interrupt controller (NVIC)

The STM32L4R5xx, STM32L4R7xx and STM32L4R9xxdevices embed a nested vectored

interrupt controller which is able to manage 16 priority levels, and to handle up to 94

maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4.

The NVIC benefits are the following:

•

Closely coupled NVIC gives low latency interrupt processing

•

Interrupt entry vector table address passed directly to the core

•

Allows early processing of interrupts

•

Processing of late arriving higher priority interrupts

•

Support for tail chaining

•

Processor state automatically saved

•

Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

3.18.2

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 36 edge detector lines used to generate

interrupt/event requests and to wake-up the system from the Stop mode. Each external line

can be independently configured to select the trigger event (rising edge, falling edge, both)

and can be masked independently.

A pending register maintains the status of the interrupt requests. The internal lines are

connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an

external line with a pulse width shorter than the internal clock period. Up to 114 GPIOs can

be connected to the 16 external interrupt lines.

STM32L4R9ZIT6STR Datasheet(PDF) 44 Page - STMicroelectronics