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STM32WB55CCU6ATR Datasheet(PDF) 24 Page - STMicroelectronics

Part # STM32WB55CCU6ATR
Description  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5 and 802.15.4 radio solution
PDF  193 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WB55CCU6ATR Datasheet(HTML) 24 Page - STMicroelectronics

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Functional overview
STM32WB55xx STM32WB35xx
24/193
DS11929 Rev 10
It integrates a 2.4 GHz RF transceiver and a powerful Cortex®-M0+ core, on which a
complete power-optimized stack for Bluetooth® Low Energy protocol runs, providing
master / slave role support
GAP: central, peripheral, observer or broadcaster roles
ATT/GATT: client and server
SM: privacy, authentication and authorization
L2CAP
Link layer: AES-128 encryption and decryption
In addition, according to Bluetooth® specification v5.0, the BLE block provides:
Multiple roles simultaneous support
Master/slave and multiple roles simultaneously
LE data packet length extension (making it possible to reach 800 kbps at application
level)
LE privacy 1.2
LE secure connections
Flexible Internet connectivity options
High data rate (2 Mbps)
The device allows the applications to meet the tight peak current requirements imposed by
the use of standard coin cell batteries. When the high efficiency embedded SMPS
step-down converter is used, the RF front end consumption (Itmax) is only 8.1 mA at the
highest output power (+6 dBm).
The power efficiency of the subsystem is optimized: while running with the radio and the
applicative cores simultaneously using the SMPS, the Cortex®-M4 core consumption
reaches 53 µA / MHz in active mode.
Ultra-low-power sleep modes and very short transition time between operating modes result
in very low average current consumption during real operating conditions, resulting in longer
battery life.
The BLE block integrates a full bandpass balun, thus reducing the need for external
components.
The link between the Cortex®-M4 application processor (CPU1) running the application, and
the BLE stack running on the dedicated Cortex®-M0+ (CPU2) is performed through a
normalized API, using a dedicated IPCC.



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