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STM32L552CCT3PXXX Datasheet(PDF) 67 Page - STMicroelectronics

Part # STM32L552CCT3PXXX
Description  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU, 165 DMIPS, up to 512 KB Flash memory, 256 KB SRAM, SMPS
PDF  340 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L552CCT3PXXX Datasheet(HTML) 67 Page - STMicroelectronics

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DS12737 Rev 6
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STM32L552xx
Functional overview
78
3.28
True random number generator (RNG)
The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a
non-deterministic random bit generator (NDRBG).
The true random number generator:
•
delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage,
•
can be used as entropy source to construct a non-deterministic random bit generator
(NDRBG),
•
produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise),
•
embeds start-up and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management,
•
can be disabled to reduce power consumption, or enabled with an automatic low-power
mode (default configuration),
•
has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated, and the write accesses are ignored).
3.29
HASH hardware accelerator (HASH)
The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-
1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the
HMAC (keyed-hash message authentication code) algorithm suitable for a variety of
applications.
It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256
algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for
messages of up to (264 - 1) bits, while the HMAC algorithms provide a way of authenticating
messages by means of hash functions. The HMAC algorithms consist in calling the SHA-1,
SHA-224, SHA-256 or MD5 hash function twice.
3.30
Timers and watchdogs
The devices include two advanced control timers, up to nine general-purpose timers, two
basic timers, two low-power timers, two watchdog timers and a SysTick timer.
Table 16 compares the features of the advanced control, general-purpose and basic timers.



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