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STM32L4R9ZIT6PXXX Datasheet(PDF) 17 Page - STMicroelectronics |
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STM32L4R9ZIT6PXXX Datasheet(HTML) 17 Page - STMicroelectronics |
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17 / 307 page  DS12023 Rev 5 17/307 STM32L4R5xx, STM32L4R7xx and STM32L4R9xx Description 65 Figure 1. STM32L4R5xx, STM32L4R7xx and STM32L4R9xx block diagram Note: AF: alternate function on I/O pins. MSv49327V2 USB OTG Flash up to 2 MB Flexible static memory controller (FSMC): SRAM, PSRAM, NOR Flash, NAND Flash GPIO PORT A AHB/APB2 EXT IT. WKUP 114 AF PA[15:0] TIM1 / PWM 3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF USART1 RX, TX, CK,CTS, RTS as AF SPI1 MOSI, MISO, SCK, NSS as AF MOSI, MISO, SCK, NSS as AF DAC1_OUT ITF WWDG RTC_TS OSC32_IN OSC32_OUT VDDA, VSSA VDD, VSS, NRST smcard irDA 16b VBAT = 1.55 to 3.6 V SCL, SDA, SMBA as AF JTAG & SW ARM Cortex-M4 120 MHz FPU NVIC ETM MPU TRACECLK TRACED[3:0] DMA2 CLK, NE[4:1], NL, NBL[1:0], A[25:0], D[15:0], NOE, NWE, NWAIT, NCE, INT as AF, FRAM RNG DP DM ID, VBUS, SOF @ VDDA BOR Supply supervision PVD, PVM Int reset XTAL 32 kHz MAN A G T RTC Standby interface IWDG @VBAT @ VDD @VDD AWU Reset & clock control VDD = 1.71 to 3.6 V VSS Voltage regulator 3.3 to 1.2 V VDD Power management @ VDD RTC_TAMPx Backup register TIM15 2 channels, 1 compl. channel, BKIN as AF DAC1 DAC2 TIM6 TIM7 TIM2 TIM3 TIM4 TIM5 USART2 USART3 I2C1/SMBUS D-BUS SRAM1 192 KB SRAM2 64 KB NJTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO I-BUS S-BUS DMA1 PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] PH[15:0] GPIO PORT B GPIO PORT C GPIO PORT D GPIO PORT E GPIO PORT F GPIO PORT G GPIO PORT H TIM8 / PWM 16b 16b TIM16 16b TIM17 16b 3 compl. Channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF 1 channel, 1 compl. channel, BKIN as AF 1 channel, 1 compl. channel, BKIN as AF DAC2_OUT 16b 16b SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF MOSI, MISO, SCK, NSS as AF RX, TX, CTS, RTS as AF RX, TX, CTS, RTS as AF RX, TX, CK, CTS, RTS as AF RX, TX, CK, CTS, RTS as AF smcard irDA smcard irDA 32b 16b 16b 32b 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF AHB/APB1 OSC_IN OSC_OUT XTAL OSC 4- 16MHz 8 analog inputs common to the ADC VREF+ US AR T 2 M B p s Temperature sensor SAI1 MCLK_A, SD_A, FS_A, SCK_A, EXTCLK MCLK_B, SD_B, FS_B, SCK_B as AF SAI2 MCLK_A, SD_A, FS_A, SCK_A, EXTCLK MCLK_B, SD_B, FS_B, SCK_B as AF DFSDM SDCKIN[7:0], SDDATIN[7:0], SDCKOUT,SDTRIG as AF Touch sensing controller 8 Groups of 4 channels max as AF OUT, INN, INP LPUART1 LPTIM1 LPTIM2 RX, TX, CTS, RTS as AF IN1, IN2, OUT, ETR as AF IN1, OUT, ETR as AF RC HSI RC LSI PLL 1&2&3 MSI OctoSPI1 memory interface IO[7:0], CLK, NCS. DQS @ VDDUSB COMP1 INP, INN, OUT COMP2 INP, INN, OUT @ VDDA RTC_OUT VDDIO, VDDUSB CRC OUT, INN, INP I2C2/SMBUS I2C3/SMBUS OpAmp1 SPI3 SPI2 UART5 UART4 AHB2 120 MHz OpAmp2 @VDDA Firewall VREF Buffer @ VDDA @ VDD Camera Interface HSYNC, VSYNC, PIXCLK, D[13:0] CHROM-ART DMA2D PI[11:0] GPIO PORT I TX, RX as AF bxCAN1 SCL, SDA, SMBA as AF I2C4/SMBUS OctoSPI2 memory interface LCD - TFT SRAM3 384 KB ITF ADC1 @ VDDA DSI Host DSI_D0 P/N DSI_D1 P/N DSI_CK P/N VDD12DSI, VDDSI, VSSDSI VCAPDSI DSI_TE LCD_R[7:0], LCD_G[7:0], LCD_B[7:0], LCD_HSYNC, LCD_VSYNC, LCD_DE, LCD_CLK Chrom-GRC (GFXMMU) SDIO / MMC D[7:0] CMD, CK as AF |
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