Fact Sheet 01.000

November 2011

These specifications are subject to change without notice.

11/28/2011

© 2011 Greenliant Systems

2

S71408-F

GLS55LD040M

PATA NAND Controller

1.0

GENERAL DESCRIPTION

The GLS55LD040M PATA NAND Controller contains a microcontroller and a flash file system integrated in a

TFBGA package. Refer to Figure 2-1 for the PATA NAND Controller block diagram. The controller interfaces with

the host system allowing data to be written to and read from the flash media.

1.1

Optimized PATA NAND Controller

The heart of the flash drive is the PATA NAND

Controller which translates standard ATA signals into

flash media data and control signals. The following

components

contribute

to

the

PATA

NAND

Controller’s operation.

1.1.1

Microcontroller Unit (MCU)

The 32 bit RISC MCU transfers the ATA/IDE

commands into required flash media operations.

1.1.2

Internal Direct Memory Access (DMA)

The PATA NAND Controller uses internal DMA

allowing instant data transfer from buffer to flash

media. This implementation eliminates microcontroller

overhead associated with the traditional, firmware-

based approach, thereby increasing the data transfer

rate.

1.1.3

Power Management Unit (PMU)

The power management unit controls the power

consumption of the PATA NAND Controller. The PMU

dramatically reduces the power consumption of the

PATA NAND Controller by putting the part of the

circuitry that is not in operation into sleep mode. The

PMU is designed so that it has zero wake-up latency

when using the internal clock.

1.1.4

SRAM Buffer

A

contributor

to

the

PATA

NAND

Controller

performance is an SRAM buffer. The buffer optimizes

the Host’s data transfer from/to and to/from the flash

media.

1.1.5

Embedded Flash File System

The embedded flash file system is an integral part of

the PATA NANDrive. It contains MCU firmware that

performs the following tasks:

1.

Translates host side signals into flash media

writes and reads

2.

Provides advanced flash media wear leveling to

spread the flash writes to increase the longevity

of flash media

3.

Keeps track of data file structures

4.

Manages

system

security for

the

selected

protection zones

5.

Stores the data in Flash media upon completion

of

a

Write

command.

The

PATA

NAND

Controller

does

not

perform

Post-Write

operations, except for when the Write cache is

enabled by the Host command.

1.1.6

Media Interface Block (MIB)

The GLS55LD040M contains two Media Interface

Blocks, MIB0 and MIB1. The MIB work independently

to transfer data to and from the NAND Flash media.

Each MIB controls two 8-bit channels.

Each Media Interface Block has three functions: DMA,

ECC and Programmable Multi-tasking NAND Interface.

1.1.7

Programmable, Multi-tasking Interface

The multi-tasking interface enables fast, sustained

write performance by allowing multiple Read, Program,

and Erase operations to multiple flash media devices.

The ease with which the NAND interface can be

programmed enables the quick support of new NAND

devices.

1.1.8

Error Correction Code (ECC)

The

GLS55LD040M

utilizes

24-bit,

BCH

Error

detection Code (EDC) and Error Correction Code

(ECC) algorithms. The ECC engine can provide,

depending on settings, 6 or 12 bits of ECC for each

512-Byte block of data, and 12 or 24 bits of ECC for

each 1KByte of data.

The ECC encoding and decoding operations occur

during the data transfer.

1.1.9

Serial Communication Interface (SCI)

The Serial Communication Interface (SCI) is designed

to

provide

trace

information

during

debugging

processes. To aid in validation, always provide the

SCI access to PCB design.

1.1.10 External Clock

The

GLS55LD040M

supports

an

external

clock

interface (XCLKI) that is enabled, or disabled, by the

external clock enable (XCLKEN) input signal. With a

4.7K

ohm

pull-down

resistor

connected

to

the

XCLKEN pin, and a 6.0 MHz external oscillator or

clock source present at the XCLKI input pin, the

GLS55LD040M uses the external oscillator as the

internal clock reference.