VD6640 datasheet(104/126 Pages) STMICROELECTRONICS

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VG6640, VD6640

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DocID023597 Rev 11

11.3

Power management

11.3.1

Power-up procedure

The digital and analog supply voltages can be powered up in any order.

If VCORE is supplied externally, XSHUTDOWN must remain LO to disable the internal 1V2

regulator.

The EXTCLK clock can either be initially low and then enabled during reset or EXTCLK can

be a free running clock.

On power-up, the host must issue a reset to ensure that the register values are initialized

correctly to their default values.

Table 60. Power-up sequence timing constraints

Symbol

Parameter

Minimum

Maximum

Units

VANA rising to VDIG rising

VANA and VDIG may rise in any

order, the rising edge separation can

vary from 0 ns to indefinite

VDIG rising to VANA rising

VANA/VDIG to RESET_N rising

RESET_N must not rise before both

power supplies (VDIG and VANA) are

stable (to within ±5%)

XSHUTDOWN to RESET_N rising

RESET_N to first I2C transaction

247000

clock periods

EXTCLK_XTAL1(1) to RESET_N

rising

clock periods

Issuing the streaming mode

command to first frame start

sequence(2)

10 + coarse

integration time

VDIG - External 1.2V rising(3)

100

1. When using an external clock. Not valid when using an external crystal.

2. Dependent on the image sensor clock frequency and the coarse exposure setting. A fast clock speed and zero exposure

will result in the shortest startup time.

3. If the 1.2V rises before VDIG then it pulls up VDIG through a substrate diodein the on-chip VCORE regulator.

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