STI5500 datasheet(10/11 Pages) STMICROELECTRONICS

10 / 11 page

NFI

NTI

The ST20 arbitor can make two types of requests

into SDRAM, a single word access (32-bits) or a

burst access of 4 x 32-bit words. The following table

summerizes the different types of accesses by

source and destination (see Table 1).

Data is moved around the device using a number

of general purpose DMA engines which are kicked

off by the CPU at a certain address and are then

autonomous. In a typical application data will arrive

via the front-end interface (a transport stream in a

set-top application or a program / sector stream in

a DVD application (see Table 1).

The link interface has a built in programmable DMA

multichannel engine which can be used to direct

the data to any memory or memory mapped periph-

eral. In the case of a set-top application a DMA

destination can be defined for each pid so for

audio/video (PES) data this destination would be

the compressed data FIFOs which are mapped into

the ST20 memory system at specific addresses.

For program specific information (EPG etc) this

data my be sent to an external buffer in SDRAM or

a memory on the external ST20 EMI.

In a DVD system the incoming sector stream data

would be sent, using the DMA in the front end

interface to a track buffer which could be either in

external DRAM off the ST20 EMI or in shared

SDRAM. This is automatic and needs no CPU

intervention appart from an initial configuration.

The track buffer is then parsed in software and two

general purpose DMAs can be used to transfer

blocks of data from the track buffer to the com-

pressed data FIFOs to be decoded. In a set-top box

application a transport stream can be split by pid

into many component streams.

The video/audio streams would be directly sent to

the CD fifos using a non-incremental DMA transfer.

Other streams such as EPG data can be stored as

a circular buffer in another memory space using an

incremental DMA.

III - INTERNAL CIRCUIT DESCRIPTION (continued)

Table 1

Source

SMI/SDRAM

ST20 EMI

Internal SRAM

Compressed Data/Reg. Port

CPU

Single Word

Caches

Burst

Single Word

n/a

Link Interface

Burst/Single

Single

DMA Engines

Single

Video Decoder

Large Bursts

n/a

Audio Decoder

Large Bursts

n/a

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