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SLAC Products
21
Master Clock
Notes:
1. The PCM clock frequency must be an integer multiple of the frame sync frequency. The maximum allowable PCM clock
frequency is 4.096 MHz. The actual PCM clock rate is dependent on the number of channels allocated within a frame. The
minimum clock frequency is 256 kHz.
2. t
TSO is defined as the time at which the output achieves the open circuit condition.
3. There is a special conflict detection circuitry that will prevent high-power dissipation from occurring when the DX pins of two
QSLAC-NP devices are tied together and one QSLAC-NP device starts to transmit before the other has gone into a
high-impedance state.
SWITCHING WAVEFORMS
Input and Output Waveforms for AC Tests
Master Clock Timing
No.
Symbol
Parameter
Min
Typ
Max
Units
38
A
MCY
Master Clock Accuracy
–100
+100
ppM
39
t
MCR
Rise Time of Clock
15
ns
40
t
MCF
Fall Time of Clock
15
ns
41
t
MCH
MCLK High Pulse Width
97
ns
42
t
MCL
MCLK Low Pulse Width
97
ns
Test
Points
2.0
0.8
2.0
0.8
2.4
0.45
19256A-015
38
39
42
41
40
20031A-005
V
IH
V
IL
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