9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

In this application, a 2-input XOR gate is used as a phase difference detector as shown in Typical application

block diagram. The remaining three gates can be used for other applications in the system, or the inputs can be

grounded and the channels left unused.

The SN74HCS86-Q1 is used to identify phase difference between a reference clock and another input clock.

Whenever the clock states are different, the XOR output will pulse HIGH until the clocks return to the same state.

The output is fed into a low-pass filter to obtain a DC representation of the phase difference.

Typically, clock signals have fast transition rates, but additional filtering can be added to the clock signals which

can lead to slower transitions rates. This makes the SN74HCS86-Q1 ideal for the application because it has

Schmitt-trigger inputs that do not have input transition rate requirements.

9.2 Typical Application

C

R

Output

Input Clock

Reference Clock

Figure 9-1. Typical application block diagram

9.2.1 Design Requirements

9.2.1.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The

supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.

The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all

and any transient current required for switching. The logic device can only source as much current as is provided

Absolute Maximum Ratings.

The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the

current required for switching. The logic device can only sink as much current as can be sunk into its ground

connection. Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum

Ratings.

The SN74HCS86-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting

all of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to

exceed 50 pF.

output voltage in the equation is defined as the difference between the measured output voltage and the supply

Total power consumption can be calculated using the information provided in CMOS Power Consumption and

Cpd Calculation.

SN74HCS86-Q1

SCLS763C – JULY 2019 – REVISED MARCH 2021

www.ti.com

10

Submit Document Feedback

Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: SN74HCS86-Q1