HT83XXX

Rev. 0.10

12

August 25, 2003

Preliminary

Labels

Bits

Function

C

0

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

AC

1

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the

high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z

2

Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

OV

3

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

PDF

4

PDF is cleared by system power-up or executing the

²CLR WDT² instruction. PDF is set by ex-

ecuting the

²HALT² instruction.

TO

5

TO is cleared by system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is

set by a WDT time-out.

¾

6, 7

Unused bit, read as

²0²

Status Register

Interrupts

The HT83XXX provides two 8-bit programmable timer

interrupts, and a time base interrupt. The Interrupt Con-

trol registers (INTC:0BH) contain the interrupt control

bits to set to enable/disable and the interrupt request

flags.

Once an interrupt subroutine is serviced, all other inter-

rupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may happen during this interval but

only the interrupt request flag is recorded. If a certain in-

terrupt needs servicing within the service routine, the

EMI bit and the corresponding INTC bit may be set to al-

low interrupt nesting. If the stack is full, the interrupt re-

quest will not be acknowledged, even if the related

interrupt is enabled, until the SP is decremented. If im-

mediate service is desired, the stack must be prevented

from becoming full.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack and then

branching to subroutines at the specified location(s) in

the program memory. Only the program counter is

pushed onto the stack. The programmer must save the

contents of the register or status register (STATUS) in

advance if they are altered by an interrupt service pro-

gram which corrupts the desired control sequence.

The Internal Timer Counter 0 Interrupt is initialized by

setting the timer counter 0 interrupt request flag (T0F:bit

5 of INTC), caused by a timer counter 0 overflow. When

the interrupt is enabled, and the stack is not full and the

T0F bit is set, a subroutine call to location 08H will occur.

The related interrupt request flag (T0F) will be reset and

the EMI bit cleared to disable further interrupts.

The Internal Timer Counter 1 Interrupt is initialized by

setting the timer counter 1 interrupt request flag (T1F:bit

6 of INTC), caused by a timer counter 1 overflow. When

the interrupt is enabled, and the stack is not full and the

T1F bit is set, a subroutine call to location 0CH will oc-

cur. The related interrupt request flag (T1F) will be reset

and the EMI bit cleared to disable further interrupts.

Time Base Interrupt is triggered by set INTC.1 (ETBI)

which sets the related interrupt request flag (TBF:bit 4 of

INTC). When the interrupt is enabled, and the stack is

not full and the external interrupt is active, a subroutine

call to location 04H will occur. The interrupt request flag

(TBF) and EMI bits will be cleared to disable other inter-

rupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgment are held until the RETI instruc-

tion is executed or the EMI bit and the related interrupt

control bit are set to 1 (of course, if the stack is not full).

To return from the interrupt subroutine, the RET or RETI

instruction may be invoked. RETI will set the EMI bit to

enable an interrupt service, but RET will not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests,

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

The timer counter 0/1 interrupt request flag (T0F/T1F)

which enables timer counter 0/1 control bit (ET0I/ET1I),

the time base interrupt request flag (TBF) which enables

time base control bit (ETTBI) from the interrupt control

register (INTC:0BH) EMI, ETBI, ET0I, ET1I are used to

control the enabling/disabling of interrupts. These bits

prevent the requested interrupt begin serviced. Once

the interrupt request flags (T0F, T1F, TBF) are set, they

will remain in the INTC register until the interrupts are

serviced or cleared by a software instruction.

It is recommended that application programs do not use

CALL subroutines within an interrupt subroutine. Inter-

rupts often occur in an unpredictable manner or need to

be serviced immediately in some applications. If only