CY29973
Document #: 38-07291 Rev. *B
Page 6 of 8
Absolute Maximum Conditions [3]
Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V
Maximum Input Voltage Relative to VDD:............. VDD + 0.3V
Storage Temperature: ................................–65
°C to + 150°C
Operating Temperature: ................................–40
°C to +85°C
Maximum ESD protection ...............................................2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current:
................................................± 20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Electrical Specifications VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
VSS
–0.8
V
VIH
Input High Voltage
2.0
–
VDD
V
VPP
Peak-to-Peak Input Voltage
PECL_CLK
300
–
1000
mV
VCMR
Common Mode Range PECL_CLK[4]
VDD – 2.0
–
VDD – 0.6
V
IIL
Input Low Current[5]
–
–
–120
µA
IIH
Input High Current[5]
––
120
µA
VOL
Output Low Voltage[6]
IOL = 20 mA
–
–
0.5
V
VOH
Output High Voltage[6]
IOH = –20 mA
2.4
–
–
V
IDDQ
Quiescent Supply Current
–
10
15
mA
IDDA
PLL Supply Current
VDD only
–
15
20
mA
IDD
Dynamic Supply Current
QA and QB @ 60 MHz,
QC @ 120 MHz, CL=30 pF
–
225
–
mA
QA and QB @ 25 MHz,
QC @ 50 MHz, CL=30 pF
–
125
–
Cin
Input Pin Capacitance
–
4
–
pF
ZOUT
Output Impedance
15
18
22
Ω
AC Electrical Specifications VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C [7]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Tr/Tf
TCLK Input Rise/Fall
–
3.0
ns
Fref
Reference Input Frequency
Note 8
–
Note 8
MHz
FrefDC
Reference Input Duty Cycle
25
–
75
%
Fvco
PLL VCO Lock Range
200
–
480
MHz
Tlock
Maximum PLL lock Time
–
–
10
ms
Tr/Tf
Output Clocks Rise/Fall Time[9]
0.8V to 2.0V
0.15
–
1.2
ns
Fout
Maximum Output Frequency
Q (
÷2)
–
–
125
MHz
Q (
÷4)
–
–
120
Q (
÷6)
–
–
80
Q (
÷8)
–
–
60
FoutDC
Output Duty Cycle[9]
TCYCLE/2 – 750
–
TCYCLE/2 + 750
ps
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range
and the input lies within the VPP specification.
5. Inputs have pull-up/pull-down resistors that effect input current.
6. Driving series or parallel terminated 50
Ω (or 50Ω to VDD/2) transmission lines.
7. Parameters are guaranteed by design and characterization. Not 100% tested in production.
8. Maximum and minimum input reference is limited by VC0 lock range.
9. Outputs loaded with 30pF each.
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