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HM6100 Datasheet(PDF) 4 Page - Shenzhen Huazhimei Semiconductor Co., Ltd |
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HM6100 Datasheet(HTML) 4 Page - Shenzhen Huazhimei Semiconductor Co., Ltd |
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4 / 6 page ![]() 4 LBI Vdown t1 Vup LBO Figure 3 Timing waveform Applications Information R1 and R2 Selection LBI pin senses the battery voltage via the resistor divider formed by R1 and R2 in Figure 1 and Figure 2. Choosing the proper R1 and R2 values is a balance between accuracy and power consumption. The leakage current into LBI pin travels through the resistor divider and introduce an error, If extremely high resistor values are used, the leakage current introduces a significant error; While with extremely low resistor values, the error becomes negligible, but the resistive divider draws more power from the battery than necessary and shortens battery life. The battery voltage at which LBO should activate is calculated by the following equation: Where, ILBI is the leakage current into LBI pin Vrth is the rising threshold From the above equation, if ILBI=5nA, R1=2MΩ, then the error is about 10mV So the maximum R1 value should be decided by the acceptable error, and the minimum value should be decided by the battery power consumption due to R1 and R2’s presence. Adding External Capacitance to Enhance Noise Immunity If monitoring voltages in a noisy environment, add a bypass capacitor of 0.1μF from battery terminal to GND as close as possible to the device. For systems with large transients, additional capacitance may be required. A small capacitor (<1nF) from LBI pin to GND may provide additional noise immunity. Negative-Going LBI Transients In addition to issuing a low output at LBO pin during power-up, power-down, and brownout conditions of the monitored voltage, the HM6100 is relatively immune to short-duration negative-going LBI transients (glitches). As the magnitude of the transient increases (goes farther below the down trip point), the maximum allowable pulse width decreases. Typically, a LBI transient that goes 35mV below the down trip point and lasts 10µs or less will not cause a low LBO output. A bypass capacitor from LBI pin to GND provides additional transient immunity. Ensuring a Valid LBO Down to VCC = 0 When VCC falls below 1.15V, HM6100 LBO output no longer sinks current—it becomes an open circuit. Therefore, high-impedance CMOS logic inputs connected to LBO can drift to undetermined voltages. This HM6100 Shenzhen H&M Semiconductor Co.Ltd http://www.hmsemi.com |
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