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Data Sheet

ADPA7009CHIP

Rev. 0 | Page 19 of 28

APPLICATIONS INFORMATION

The ADPA7009CHIP is a GaAs, pHEMT, MMIC power

amplifier. Capacitive bypassing is required for all primary and

alternate VGGx and VDDx pads. VGG1 and VGG2 are the gate bias

pads for the amplifier. VDD1, VDD2, VDD3, and VDD4 are the drain

bias pads for the amplifier.

All measurements for this device were taken using the primary

application circuit (see Figure 66) and were configured as

shown in the assembly diagram (see Figure 79).

The recommended bias sequence during power-up is as

follows:

1. Connect GND to RF and dc ground.

2. Set the gate bias voltages, VGG1 and VGG2, to −1.5 V.

3. Set all the drain bias voltages, VDDx, to 5 V.

4. Increase the gate bias voltages, VGG1 and VGG2, to achieve an

IDQ of 750 mA.

5. Apply the RF signal.

The recommended bias sequence during power-down is as

follows:

1. Turn off the RF signal.

2. Decrease the primary gate bias voltages, VGG1 and VGG2, to

−1.5 V to achieve IDQ = 0 mA (approximately).

3. Decrease all the drain bias voltages to 0 V.

4. Increase the gate bias voltage to 0 V.

The VDD = 5 V and IDQ = 750 mA bias conditions are

recommended to optimize overall performance. Unless

otherwise noted, the data shown was taken using the

recommended bias conditions. Operation of the ADPA7009CHIP

at different bias conditions may provide performance that

differs from what is shown in Table 1 to Table 4. Biasing the

ADPA7009CHIP for higher drain current typically results in

higher P1dB and gain at the expense of increased power

consumption (see Table 9).

TYPICAL APPLICATION CIRCUIT

Figure 66 shows the primary application circuit. Figure 67

shows the alternate typical application circuit.

Table 9. Power Selection Table1, 2

IDQ (mA)

Gain (dB)

P1dB (dBm)

Output IP3 (dBm)

PDISS (W) at PSAT

VGGx (V)

650

20.33

27.57

37.07

3.25

−0.68

750

21.02

27.93

34.83

3.75

−0.63

850

21.52

28.17

32.69

4.25

−0.59

950

22.02

28.34

31.19

4.75

−0.54

Data taken at the following nominal bias conditions: VDD = 5 V, TA = 25°C, and frequency = 36 GHz.

Adjust VGGx from −1.5 V to 0 V to achieve the desired drain current.

VGG1

4.7µF

0.01µF

100pF

4.7µF

0.01µF

100pF

VDD1,

VDD2

RFIN

RFOUT

VDET

VREF

100kΩ

+5V

10kΩ

–

VOUT = VREF – VDET

–5V

10kΩ

SUGGESTED CIRCUIT

Figure 66. Primary Application Circuit

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