VBUS053CZ-HAF datasheet(2/7 Pages) VISHAY

2 / 7 page

VBUS053CZ-HAF

www.vishay.com

Vishay Semiconductors

Rev. 1.7, 08-Jan-2019

Document Number: 85200

For technical questions, contact: ESDprotection@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Note

• Ratings at 25 °C ambient temperature, unless otherwise specified

Note

• Ratings at 25 °C ambient temperature, unless otherwise specified

APPLICATION NOTE

The VBUS053CZ-HAF is intended as an ESD protection and transient voltage suppressor for one USB-OTG port.



The LLP75-7L package contains two separate dies which are mounted on a common ground plane (pin 7).



The high-speed data lines D-, D+ and ID, are connected to any of the pins no. 1 to 3. As long as the signal voltage on the data

lines is between the ground- and the 5 V working range, the low capacitance PN-diodes offer a very high isolation to ground

and to the other data lines. But as soon as any transient signal like an ESD signal, exceeds this working range of 5 V in either

the positive or negative direction, one of the PN-diodes gets into the forward mode and clamps the transient either to ground

or to the avalanche break through level. An extra avalanche diode (separate die) clamps the supply line voltage (VBUS at pin 6)

above the 28 V working range to ground (pin 7). Due to the “two die construction” the VBUS line has a very high isolation to the

data lines. In case of a destructive transient signal, i.e. coming from a charger, the data lines will not be influenced.

Remark:

The input pins no. 1, 2 and 3 are symmetrical. Each of the data signals D-, D+ and ID can be connected to pin 1, 2 or 3

ELECTRICAL CHARACTERISTICS VBUS053CZ-HAF All inputs (pin 1, 2, and 3) to ground (pin 7)

PARAMETER

TEST CONDITIONS/REMARKS

SYMBOL

MIN.

TYP.

MAX.

UNIT

Protection paths

Number of line which can be protected

Nchannel

lines

Reverse working voltage

Reverse stand-off voltage

VRWM

5.5

Reverse voltage

at IR = 0.1 μA

5.5

Reverse current

at VR = 3.3 V

0.02

μA

at VR = 3.3 V; T = 65 °C

0.085

μA

at VR = VRWM = 5.5 V

0.1

μA

Forward voltage

at IF = 15 mA

0.7

1.2

Reverse breakdown voltage

at IR = 1 mA

VBR

6.5

Reverse clamping voltage

at IPP = 1 A; acc. IEC 61000-4-5

-10

at IPP = 3 A; acc. IEC 61000-4-5

-15

Forward clamping voltage

at IF = 3 A; acc. IEC 61000-4-5

-3.4

4.1

Line capacitance

Test pin at VR = 0 V;

any other I/O pin at VR = 3.3 V; f = 1 MHz

-0.7

Line to line capacitance

Among pins 1, 2 and 3

at VR = 0 V; f = 1 MHz

0.35

0.5

Line symmetry

Difference of the line capacitance

dCD

0.1

ELECTRICAL CHARACTERISTICS VBUS (pin 6) to ground (pin 7)

PARAMETER

TEST CONDITIONS/REMARKS

SYMBOL

MIN.

TYP.

MAX.

UNIT

Protection paths

Number of line which can be protected

Nchannel

lines

Reverse working voltage

Reverse stand-off voltage

VRWM

Reverse voltage

at IR = 0.1 μA

Reverse current

at VR = VRWM = 28 V

100

Forward voltage

at IF = 10 mA

0.60.750.9

Reverse breakdown voltage

at IR = 1 mA

VBR

Reverse clamping voltage

at IPP = 1 A; acc. IEC 61000-4-5; T = 25 °C

-37

at IPP = 3 A; acc. IEC 61000-4-5; T = 25 °C

-42

Forward clamping voltage

at IF = 3 A; acc. IEC 61000-4-5

2.2

Line capacitance

at VR = 0 V; f = 1 MHz

-31

nc.

D-

D+

GND

BUS

21103

(pinning top view)

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