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PSD813F1AV-12MIT Datasheet(PDF) 81 Page - STMicroelectronics |
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PSD813F1AV-12MIT Datasheet(HTML) 81 Page - STMicroelectronics |
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81 / 110 page  81/110 PSD813F1V Figure 41. Input to Output Disable / Enable Figure 42. Combinatorial Timing PLD Table 47. CPLD Combinatorial Timing (5V devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. 2. ZPSD versions only. Symbol Parameter Conditions -90 -12 -15 Fast PT Aloc Turbo Off2 Slew rate1 Unit Min Max Min Max Min Max tPD CPLD Input Pin/ Feedback to CPLD Combinatorial Output 25 30 32 + 2 + 10 – 2 ns tEA CPLD Input to CPLD Output Enable 26 30 32 + 10 – 2 ns tER CPLD Input to CPLD Output Disable 26 30 32 + 10 – 2 ns tARP CPLD Register Clear or Preset Delay 26 30 33 + 10 – 2 ns tARPW CPLD Register Clear or Preset Pulse Width 20 24 29 + 10 ns tARD CPLD Array Delay Any macrocell 16 18 22 + 2 ns tER tEA INPUT INPUT TO OUTPUT ENABLE/DISABLE AI02863 tPD CPLD INPUT CPLD OUTPUT ai09228 |
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