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Data Sheet

ADAQ4001

THEORY OF OPERATION

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Rev. 0 | 21 of 38

CIRCUIT INFORMATION

The ADAQ4001 SiP is a fast, precision DAQ signal chain that uses

SAR architecture. As shown in Figure 1, the ADAQ4001 μModule

DAQ solution contains a high bandwidth, fully differential ADC

driver, a low noise reference buffer, and a 16-bit SAR ADC, along

with the critical precision passive components required to achieve

optimized performance with pin-selectable gain options of 0.454,

0.909, 1, or 1.9. All active components in the circuit, including

iPassives thin film resistors with ±0.005% matching, are designed

by Analog Devices and are factory calibrated to achieve a high

degree of specified accuracy and minimize temperature dependent

error sources.

The ADAQ4001 is capable of converting 2,000,000 samples per

second (2 MSPS). The ADAQ4001 has a valid first conversion after

being powered down for long periods that can reduce power con-

sumed in applications where the ADC does not convert constantly.

The ADAQ4001 offers a significant reduction in form factor and total

cost of ownership compared to traditional discrete signal chains

from a selection of individual components, PCB size, and manufac-

turing perspective, while still providing the flexibility to adapt to a

wide array of applications.

The ADAQ4001 incorporates a fully differential, high speed ADC

driver with integrated precision resistors. The precision resistors

can be pin strapped to achieve different gains for the fully differen-

tial ADC driver, which allows the user to match the input signal

range. The fully differential ADC driver can be used in a differential

manner or to perform a single-ended to differential conversion for a

single-ended input.

The fast conversion time of the ADAQ4001, along with turbo mode,

allows low clock rates to read back conversions, even when the

ADAQ4001 is running at its maximum throughput rate. Note that

for the ADAQ4001, the full throughput rate of 2 MSPS can be

achieved only with turbo mode enabled. Because the ADAQ4001

has on-board conversion clocks, the serial clock (SCK) is not

required for the conversion process.

The ADAQ4001 interfaces to any 1.8 V to 5 V digital logic family.

The device is housed in a 7 mm × 7 mm, 0.80 mm pitch, 49-ball

CSP_BGA that provides significant space savings and allows flexi-

ble configurations.

TRANSFER FUNCTIONS

The ideal transfer characteristics for the ADAQ4001 are shown in

Figure 40 and Table 10.

Figure 40. ADC Ideal Transfer Function (FSR Is Full-Scale Range)

Table 10. Output Codes and Ideal Input Voltages

Description

Analog Inputs

Digital Output Code1

(Twos Complement, Hex)

Span Compression Disabled

Span Compression Enabled

FSR − 1 LSB

(32,767 × VREF)/(32,768 × G)

(32,767 × 0.8 × VREF)/(32,768 × G)

0x7FFF2

Midscale + 1 LSB

VREF/(32,768 × G)

0.8 × VREF/(32,768 × G)

0x0001

Midscale

0 V

0x0000

Midscale − 1 LSB

−VREF/(32,768 × G)

−0.8 × VREF/(32,768 × G)

0xFFFF

−FSR + 1 LSB

−(32,767 × VREF)/(32,768 × G)

−(32,767 × 0.8 × VREF)/(32,768 × G)

0x8001

−FSR

−VREF × G

−0.8 × VREF × G

0x80003

1 This output code assumes that the negative input, IN−, of the ADC driver is being driven.

2 This output code is also the code for an overranged analog input (IN+ − IN− above VREF with the span compression disabled and above 0.8 × VREF with the span

compression enabled).

3 This output code is also the code for an underranged analog input (IN+ − IN− below −VREF with the span compression disabled and below 0.8 × −VREF with the span

compression enabled).

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