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ADGS1212BCPZ Datasheet(PDF) 3 Page - Analog Devices

Part # ADGS1212BCPZ
Description  SPI Interface, Quad SPST Switch, Low QINJ, Low CON, 짹15 V/12 V, Mux Configurable
PDF  24 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADGS1212BCPZ Datasheet(HTML) 3 Page - Analog Devices

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Data Sheet
ADGS1212
Rev. 0 | Page 3 of 24
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 1.
Parameter
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VDD to VSS
V
On Resistance, RON
120
Ω typ
VS = ±10 V, IS = −10 mA,
see Figure 24
190
230
260
Ω max
VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match Between
Channels, ∆RON
2.5
Ω typ
VS = ±10 V, IS = −10 mA
6
10
11
Ω max
On-Resistance Flatness, RFLAT (ON)
20
Ω typ
VS = −5 V/0 V/+5 V, IS = −10 mA
57
72
79
Ω max
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (OFF)
±0.02
nA typ
VS = ±10 V, VD =  10 V,
see Figure 27
±0.1
±0.6
±1
nA max
Drain Off Leakage, ID (OFF)
±0.02
nA typ
VS = ±10 V, VD =  10 V,
see Figure 27
±0.1
±0.6
±1
nA max
Channel On Leakage, ID (ON), IS (ON)
±0.02
nA typ
VS = VD = ±10 V, see Figure 23
±0.1
±0.6
±1
nA max
DIGITAL OUTPUT
Output Voltage
Low, VOL
0.4
V max
ISINK = 5 mA
0.2
V max
ISINK = 1 mA
High or Low Output Current, IOL or IOH
0.001
µA typ
Output voltage (VOUT) =
ground voltage (VGND) or VL
±0.1
µA max
Digital Output Capacitance, COUT
4
pF typ
DIGITAL INPUTS
Input Voltage
High, VINH
2
V min
3.3 V < VL ≤ 5.5 V
1.35
V min
2.7 V ≤ VL ≤ 3.3 V
Low, VINL
0.8
V max
3.3 V < VL ≤ 5.5 V
0.8
V max
2.7 V ≤ VL ≤ 3.3 V
Low or High Input Current, IINL or IINH
0.001
µA typ
VIN = VGND or VL
±0.1
µA max
Digital Input Capacitance, CIN
4
pF typ
DYNAMIC CHARACTERISTICS1
On Time, tON
375
ns typ
Load resistance (RL) = 300 Ω,
load capacitance (CL) = 35 pF
450
450
450
ns max
VS = 10 V, see Figure 32
Off Time, tOFF
125
ns typ
RL = 300 Ω, CL = 35 pF
160
180
205
ns max
VS = 10 V, see Figure 32
Break-Before-Make Time Delay, tD
205
ns typ
RL = 300 Ω, CL = 35 pF
150
ns min
VS1 = VS2 = 10 V, see Figure 31
Charge Injection, QINJ
−0.9
pC typ
VS = 0 V, source resistance (RS) = 0 Ω,
CL = 1 nF, see Figure 33
Off Isolation
−80
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 26



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