ADGS5412BCPZ datasheet(25/30 Pages) AD

25 / 30 page

Data Sheet

ADGS5412

Rev. A | Page 25 of 30

BREAK-BEFORE-MAKE SWITCHING

The ADGS5412 exhibits break-before-make switching action,

which allows the use of the device in multiplexer applications.

This configuration can be achieved by externally hardwiring the

device in the mux configuration that is required, as shown in

Figure 45.

4 × SPST

4:1 MUX

SCLK SDI CS RESET/VL

SPI

INTERFACE

Figure 45. An SPI Controlled Switch Configured into a 4:1 Mux

TRENCH ISOLATION

In the analog switch section of the ADGS5412, an insulating

oxide layer (trench) is placed between the negative channel metal-

oxide semiconductor (NMOS) and the positive channel metal-

oxide semiconductor (PMOS) transistors of each complementary

metal oxide semiconductor switch (CMOS). Parasitic junctions,

which occur between the transistors in junction isolated

switches, are eliminated, and the result is a completely latch-up

proof switch.

In junction isolation, the negative (N) and positive (P) wells of the

PMOS and NMOS transistors form a diode that is reverse-biased

under normal operation. However, during overvoltage

conditions, this diode can become forward-biased. A silicon

controlled rectifier (SCR) circuit is formed by the two transistors,

causing a significant amplification of the current that, in turn,

leads to latch-up. With trench isolation, this diode is removed,

and the result is a latch-up proof switch. The ADGS5412 analog

switch pins pass the maximum rating in the JESD78D standard

in which they are stressed with a ±500 mA pulse for 1 second.

The high voltage latch-up proof family of switches and multiplexers

provide a robust solution for instrumentation, industrial, automo-

tive, aerospace, and other harsh environments that are prone to

latch-up, which is an undesirable high current state that can

lead to device failure and which persists until the power supply

is turned off. The ADGS5412 high voltage switches allow

single-supply operation from 9 V to 40 V and dual-supply

operation from ±9 V to ±22 V.

NMOS

PMOS

P-WELL

N-WELL

BURIED OXIDE LAYER

HANDLE WAFER

TRENCH

Figure 46. Trench Isolation

DIGITAL INPUT BUFFERS

There are input buffers present on the digital inputs pins CS,

SCLK, and SDI. These buffers are active at all times. As result of

this, there will be current draw from the VL supply if SCLK or SDI

are toggling, regardless whether CS is active. For typical values of

this current draw, refer to the specification tables and

Figure 26.

ADGS5412BCPZ Datasheet(PDF) 25 Page - Analog Devices

ADGS5412BCPZ Datasheet(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Datasheet Download

Link URL