ADMV7310BCEZ datasheet(23/29 Pages) AD

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Data Sheet

ADMV7310

Rev. A | Page 23 of 29

THEORY OF OPERATION

The ADMV7310 is a fully integrated SiP, I/Q upconverter that is

made up of three functional blocks: a mixer and LO path, an

envelope detector, a VGA, and a power detector, and a power

amplifier and power detector.

MIXER AND LO PATH

The first functional block is a gallium arsenide (GaAs) I/Q

upconverter driven by a 6× LO multiplier. The 6× multiplier

allows the use of a lower frequency range LO input signal between

11.8 GHz and 12.7 GHz. The 6× multiplier is implemented using

a cascade of 3× and 2× multipliers. LO buffer amplifiers are

included on chip to allow a typical LO drive level of 4 dBm for

typical performance. The LO path feeds a quadrature splitter

followed by on-chip baluns that drive the I and Q mixer cores.

The mixer cores comprise of singly balanced passive mixers.

The RF outputs of the I and Q mixers are then summed through

an on-chip Wilkinson power combiner, which is then fed into

the second functional block.

ENVELOPE DETECTOR, VGA, AND POWER

DETECTOR

The second functional block is a VGA (see Figure 81). The

VGA utilizes multiple gain stages and staggered voltage variable

attenuation stages to form a low noise, high linearity variable

gain amplifier. The first stage of the VGA is a low noise preamp.

A portion of the signal is coupled away and further amplified

before driving an on-chip envelope detector. The envelope

detector provides an output that is proportional to the peak

envelope power of the incoming signal.

The preamp is followed by the first voltage variable attenuator in

the signal path. Then, a second stage amplifier provides additional

gain and isolation before driving the second variable attenuator

block. Three cascaded gain stages follow the second variable

attenuator.

At the output of the second stage, another coupler taps off a

small portion of the output signal. The coupled signal is

presented to an on-chip diode detector for external monitoring

of the output power. A matched reference diode, Detector 1

(DET1), is included to help correct for detector temperature

dependencies. A typical application circuit for the power

detector is shown in Figure 83.

See the Applications Information section for further details on

biasing the different blocks. The output of the VGA then feeds

into the third functional block of the ADMV7310.

POWER AMPLIFIER AND POWER DETECTOR

The third block is a power amplifier that uses four cascaded

gain stages to form the amplifier (see Figure 82). At the output

of the last stage, a coupler taps off a small portion of the output

signal. The coupled signal is presented to an on-chip diode

detector for external monitoring of the output power. A matched

reference diode, Detector 2 (DET2), is included to help correct

for detector temperature dependencies.

DET1_REF DET1_OUT

OUTPUT

ENVELOPE

DETECTOR

INPUT

VGA_CTL12

ENV_DET

Figure 81. Variable Gain Amplifier Circuit Architecture

DET2_REF

DET2_OUT

OUTPUT

INPUT

Figure 82. Power Amplifier Circuit Architecture

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