I

Unless otherwise noted, V

appearing in boldface type apply over the entire junction temperature range for operation, −30˚C to +125˚C. (Notes 2, 8, 9)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

F

CLK

Clock Frequency

400

kHz

t

BF

Bus-Free Time between Start and Stop

(Note 10)

1.3

µS

t

HOLD

Hold Time Repeated Start Condition

(Note 10)

0.6

µS

t

CLKLP

CLK Low Period

(Note 10)

1.3

µS

t

CLKHP

CLK High Period

(Note 10)

0.6

µS

t

SU

Set Up Time Repeated Start Condition

(Note 10)

0.6

µS

t

DATAHLD

Data Hold Time

(Note 10)

200

nS

t

CLKSU

Data Set Up Time

(Note 10)

200

nS

T

SU

Set Up Time for Start Condition

(Note 10)

0.6

µS

T

TRANS

Maximum Pulse Width of Spikes that Must be

Suppressed by the Input Filter of Both DATA & CLK

signals.

(Note 10)

50

nS

VDD_I

1

V

IN

V

I

In I

and the SDA pin is used for the I

need a pull-up resistor according to I

values of the pull-up resistor are determined by the capaci-

tance of the bus (typ.

∼1.8k). Signal timing specifications are

according to the I

is 400 kHz.

I

The data on SDA line must be stable during the HIGH period

of the clock signal (SCL). In other words, state of the data

line can only be changed when CLK is LOW.

20167306

I

START and STOP bits classify the beginning and the end of

the I

transitioning from HIGH to LOW while SCL line is HIGH.

STOP condition is defined as the SDA transitioning from

LOW to HIGH while SCL is HIGH. The I

generates START and STOP bits. The I

to be busy after START condition and free after STOP con-

dition. During data transmission, I

repeated START conditions. First START and repeated

START conditions are equivalent, function-wise.

20167307

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