List of figures

Figure 1.

TSB711 pin connections (top view) ...................................................... 2

Figure 2.

TSB712 pin connections (top view) ...................................................... 2

Figure 3.

TSB714 pin connections (top view) ...................................................... 3

Figure 4.

Supply current vs. supply voltage ...................................................... 10

Figure 5.

Input offset voltage distribution at VCC = 5 V TSB711A, TSB712A ................................ 10

Figure 6.

Input offset voltage distribution at VCC = 36 V TSB711A, TSB712A ............................... 10

Figure 7.

Input offset voltage vs. temperature at VCC = 5 V ........................................... 10

Figure 8.

Input offset voltage vs. temperature at VCC = 36 V .......................................... 11

Figure 9.

Input offset voltage thermal coefficient distribution at VCC = 5 V ................................. 11

Figure 10.

Channel separation vs. frequency at VCC = 36 V............................................ 11

Figure 11.

Input offset voltage vs. supply voltage ................................................... 11

Figure 12.

Input offset voltage vs. common mode voltage at VCC = 5 V TSB711A, TSB712A ..................... 11

Figure 13.

Input offset voltage vs. common mode voltage at VCC = 36 V TSB711A, TSB712A .................... 11

Figure 14.

Input bias current vs. temperature at VICM = VCC / 2 ......................................... 12

Figure 15.

Output current vs. output voltage at

VCC = 5 V ....................................... 12

Figure 16.

Input bias current vs. common mode voltage at VCC = 5 V ..................................... 12

Figure 17.

Input bias current vs. common mode voltage at VCC = 36 V .................................... 12

Figure 18.

Output current vs. output voltage at VCC = 36 V ............................................ 12

Figure 19.

Output voltage (VOH) vs. supply voltage.................................................. 12

Figure 20.

Output voltage (VOL) vs. supply voltage .................................................. 13

Figure 21.

Positive slew rate at VCC = 36 V ....................................................... 13

Figure 22.

Negative slew rate at VCC = 36 V ...................................................... 13

Figure 23.

Bode diagram at VCC = 5 V .......................................................... 13

Figure 24.

Bode diagram at VCC = 36 V ......................................................... 13

Figure 25.

Phase margin vs. output current at VCC = 5 V .............................................. 13

Figure 26.

Phase margin vs. output current at VCC = 36 V ............................................. 14

Figure 27.

Phase margin vs. capacitive load ...................................................... 14

Figure 28.

Overshoot vs. capacitive load at VCC = 36 V............................................... 14

Figure 29.

Small step response vs. time at VCC = 5 V ................................................ 14

Figure 30.

Desaturation time at low rail at VCC = 5 V................................................. 14

Figure 31.

Desaturation time at high rail at VCC = 5 V ................................................ 14

Figure 32.

Small step response vs. time at VCC = 36 V ............................................... 15

Figure 33.

Amplifier behavior close to the low rail at VCC = 36 V......................................... 15

Figure 34.

Amplifier behavior close to the high rail at VCC = 36 V ........................................ 15

Figure 35.

Noise vs. frequency at VCC = 5 V ...................................................... 15

Figure 36.

Noise vs. frequency at VCC = 36 V ..................................................... 15

Figure 37.

Noise vs. time at VCC = 36 V ......................................................... 15

Figure 38.

THD+N vs. frequency .............................................................. 16

Figure 39.

THD+N vs. output voltage ........................................................... 16

Figure 40.

PSRR vs. frequency at VCC = 10 V ..................................................... 16

Figure 41.

CMRR vs. frequency at VCC = 10 V..................................................... 16

Figure 42.

Input current limitation .............................................................. 17

Figure 43.

Rail-to-rail input stage .............................................................. 18

Figure 44.

EMIRR on In+, In- and out pins........................................................ 20

Figure 45.

Stability criteria with a serial resistor at different capacitive loads................................. 21

Figure 46.

Test configuration for RISO ........................................................... 22

Figure 47.

Low-side current sensing schematic .................................................... 24

Figure 48.

SOT23-5 package outline ........................................................... 25

TSB711, TSB711A, TSB712, TSB712A, TSB714, TSB714A

List of figures

DS12487 - Rev 6

page 34/36