7

ICS91857

0494C—08/15/05

Notes:

1.

Refers to transition on noninverting output in PLL bypass mode.

2.

Switching characteristics guaranteed for application frequency range.

3.

Static phase offset shifted by design.

Timing Requirements for DDRI-400

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Max clock frequency

2.6V ± 0.1V

60

230

MHz

Application Frequency

Range

2.6V ± 0.1V

95

220

MHz

Input clock duty cycle

40

60

%

CLK stabilization

100

µs

Switching Characteristics for DDR200/266/333

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Low-to high level

propagation delay time

1

CLK_IN to any output

3.5

ns

High-to low level propagation

delay time

1

CLK_IN to any output

3.5

ns

Output enable time

PD# to any output

3

ns

Output disable time

PD# to any output

3

ns

Period jitter

100 - 200 MHz

-75

75

ps

Half-period jitter

100 - 200 MHz

-75

75

Input clock slew rate

14

V/ns

Output clock slew rate

12

V/ns

Cycle to Cycle Jitter

1

100 - 200 MHz

-75

75

ps

Static Phase Offset

3

-50

0

50

ps

Output to Output Skew

100

ps

Pulse skew

100

ps

Timing Requirements for DDR200/266/333

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Max clock frequency

2.5V ± 0.2V @ 25°C

60

170

MHz

Application Frequency

Range

2.5V ± 0.2V @ 25°C

95

170

MHz

Input clock duty cycle

40

60

%

CLK stabilization

100

µs