92

C3017-4-98

Process C3017

Starting Material

P <100>

N+/P+ Width/Space

3.0 / 3.0

µm

Starting Mat. Resistivity

15 - 25

Ω-cm

N+ To P+ Space

12

µm

Typ. Operating Voltage

10V

Contact To Poly Space

2.5

µm

Well Type

P-well

Contact Overlap Of Diffusion

1.5

µm

Metal Layers

2

Contact Overlap Of Poly

1.0

µm

Poly Layers

2

Metal-1 Overlap Of Contact

1.0

µm

Contact Size

2.0x2.0

µm

Metal-1 Overlap Of Via

1.75

µm

Via Size

2.0x2.0

µm

Metal-2 Overlap Of Via

1.5

µm

Metal-1 Width/Space

3.5 / 2.5

µm

Minimum Pad Opening

100x100

µm

Metal-2 Width/Space

5.0 / 3.0

µm

Minimum Pad-to-Pad Spacing

5.0

µm

Gate Poly Width/Space

4.0 / 2.5

µm

Minimum Pad Pitch

80.0

µm

Special Feature of C3017 Process: P-well analog process with double metal CMOS 3.0

µm

technology.

Physical Characteristics

5

4

3

2

1

0

0123456789

10

ID vsVD, W/L = 20/4.0

n-ch Transistor IV characteristics of a 20/4.0 device

VGS = 10V

VGS = 9.0V

VGS = 8.0V

VGS = 7.0V

VGS = 6.0V

VGS = 5.0V

VGS = 4.0V

VGS = 3.0V

VGS = 2.0V

-3

-2.5

-2

-1.5

-1

-.5

0

0123456789

10

ID vsVD, W/L = 20/4.0

p-ch Transistor IV characteristics of a 20/4.0 device

VGS = -10V

VGS = -9.0V

VGS = -8.0V

VGS = -7.0V

VGS = -6.0V

VGS = -5.0V

VGS = -4.0V

VGS = -3.0V

VGS = -2.0V

Cross-sectional view of the C3017 process

Second metal

LTO

p

Field Oxide

Poly gate

p-well

VIA

Metal 1

A1

p

p

n-epi