MCP6V69-ESLASHST datasheet(19/46 Pages) MICROCHIP

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DS20006266A-page 19

MCP6V66/6U/7/9

4.2.1.3

Input Current Limits

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

into the input pins (see Section 1.1 “Absolute

Maximum

Ratings †”).

This

requirement

independent of the voltage limits discussed previously.

Figure 4-6 shows one approach to protecting these

inputs. The R1 and R2 resistors limit the possible

current in or out of the input pins (and into D1 and D2).

The diode currents will dump onto VDD.

FIGURE 4-6:

Protecting the Analog Inputs

Against High Currents.

It is also possible to connect the diodes to the left of the

R1 and R2 resistors. In this case, the currents through

the D1 and D2 diodes need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (VIN+ and

VIN-) should be very small.

A significant amount of current can flow out of the inputs

(through the ESD diodes) when the Common Mode

Voltage (VCM) is below ground (VSS) (see Figure 2-15).

4.2.2

RAIL-TO-RAIL OUTPUT

The Output Voltage Range of the MCP6V66/6U/7/9

zero-drift op amps is VDD – 5.9 mV (typical) and

VSS + 4.7 mV (typical) when RL =20kΩ is connected to

VDD/2 and VDD = 5.5V. Refer to Figures 2-17 and 2-18

for more information.

This op amp is designed to drive light loads; use

another amplifier to buffer the output from heavy loads.

4.3

Application Tips

4.3.1

INPUT OFFSET VOLTAGE OVER

TEMPERATURE

Table 1-1 gives both the linear and quadratic

temperature coefficients (TC1 and TC2) of input offset

voltage. The input offset voltage, at any temperature in

the specified range, can be calculated as follows:

EQUATION 4-1:

4.3.2

OFFSET AT POWER-UP

When these parts power up, the input offset (VOS)

starts at its uncorrected value. Circuits with high DC

gain can cause the output to reach one of the two rails.

In this case, the time to a valid output is delayed by an

output overdrive time (like tODR) in addition to the

start-up time (like tSTR).

It can be simple to avoid this extra start-up time.

Reducing the gain is one method. Adding a capacitor

across the feedback resistor (RF) is another method.

VDD

min(R1,R2)>

VSS –min(V1,V2)

2mA

VOUT

min(R1,R2)>

max(V1,V2)– VDD

2mA

MCP6V6X

VOS TA



VOS TC1TTC2T

Where:

T=TA –25°C

VOS(TA) = Input offset voltage at TA

VOS = Input offset voltage at +25°C

TC1 = Linear temperature coefficient

TC2 = Quadratic temperature coefficient

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