MCP48CMB22 datasheet(45/106 Pages) MICROCHIP

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 2019 Microchip Technology Inc.

DS20006160A-page 45

MCP48CXBXX

4.1.2

BROWN-OUT RESET

A Brown-out Reset occurs when a device had power

applied to it and that power (voltage) drops below the

specified range.

When the falling VDD voltage crosses the VPOR trip

point (BOR event), the following occurs:

• Serial Interface is disabled.

• MTP Writes are disabled.

• Device is forced into a Power-Down state

(PDxB:PDxA = ‘11’). Analog circuitry is turned off.

• Volatile DAC register is forced to 000h.

Volatile configuration bits VRxB:VRxA and GX are

forced to ‘0’.

If the VDD voltage decreases below the VRAM voltage,

all volatile memory may become corrupted.

As the voltage recovers above the VPOR/VBOR voltage,

see Section 4.1.1 “Power-on Reset” for further

details.

Serial commands not completed due to a brown-out

condition may cause the memory location to become

corrupted.

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

4.2

Device Memory

User memory includes the following types:

• Volatile Register Memory (RAM)

• Nonvolatile Register Memory (MTP)

MTP memory is present just for the MCP48CMBXX

devices and has three groupings:

• NV DAC Output Values (loaded on POR event)

• Device Configuration Memory

• General Purpose NV Memory

Each memory location is up to 16 bits wide. The

memory mapped register space is shown in Table 4-1.

The SPI interface depends on how this memory is read

and written. Refer to Section 6.0 “SPI Serial Interface

Module” and Section 7.0 “Device Commands” for

more details on reading and writing the device’s

memory.

4.2.1

VOLATILE REGISTER MEMORY

(RAM)

The MCP48CXBXX devices have volatile memory to

directly control the operation of the DACs. There are

up to five volatile memory locations:

• DAC0 and DAC1 Output Value registers

•VREF Select register

• Power-Down Configuration register

• Gain and Status register

The volatile memory starts functioning when the

device VDD is at (or above) the RAM retention voltage

(VRAM). The volatile memory will be loaded with the

default device values when the VDD rises across the

VPOR/VBOR voltage trip point.

After the device is powered-up, the user can update

the device memory. Table 4-2 shows the volatile

memory locations and their interaction due to a POR

event.

4.2.2

NONVOLATILE REGISTER

MEMORY (MTP)

This memory option is available only for the

MCP48CMBXX devices.

MTP memory starts functioning below the device’s

VPOR/VBOR trip point and, once the VPOR event

occurs, the volatile memory registers are loaded with

the corresponding MTP register memory values.

Memory addresses 0Ch through 1Fh are nonvolatile

memory locations. These locations contain the DAC

POR/BOR Wiper values, the DAC POR/BOR

configuration bits and 8 general purpose memory

locations for storing user-defined data as calibration

constants or identification numbers.

The nonvolatile wiper registers and configuration bits

determine the DAC Output and Configuration values at

the POR event.

These nonvolatile values will overwrite the factory

default values. If these MTP

addresses are

unprogrammed, the factory default values define the

output state.

The nonvolatile DAC registers enable the standalone

operation of the device (without microcontroller

control), after being programmed to the desired

values.

program

nonvolatile

memory

locations,

high-voltage source on the LAT/HVC pin is required.

Each register/MTP location can be programmed 32

times. After 32 writes, a new write operation will not be

possible and the last successful value written will

remain associated with the memory location.

The device starts writing the MTP memory cells at the

completion of the serial interface command. The high

voltage should remain present on the LAT/HVC pin

until the write cycle is complete; otherwise, the write is

unsuccessful and the location is compromised (cannot

be used again and the number of available writes

decreases by one).

To recover from an aborted MTP write operation, the

following procedure must be used:

• Write any valid value to the same address again

• Force a POR condition

• Write the desired value to the MTP location again

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