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WM8774IFT Datasheet(PDF) 25 Page - Wolfson Microelectronics plc |
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WM8774IFT Datasheet(HTML) 25 Page - Wolfson Microelectronics plc |
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25 / 42 page  Product Preview WM8774 PP Rev 1.0 June 2002 25 BIT LABEL DEFAULT DESCRIPTION 10011 Timeout Clock Disable 3 TOD 0 DAC Analogue Zero cross detect timeout disable 0 : Timeout enabled 1: Timeout disabled DAC ANALOGUE OUTPUT ATTENUATION Register bits LA and RA control the left and right channel attenuation of DAC. Register bits MASTA can be used to control attenuation of both channels. Table 8 shows how the attenuation levels are selected from the 7-bit words. L/RA[6:0] ATTENUATION LEVEL 00(hex) - ∞dB (mute) : : 1A(hex) - ∞dB (mute) 1B(hex) -100dB : : 7D(hex) -2dB 7E(hex) -1dB 7F(hex) 0dB Table 10 Analogue Volume Control Attenuation Levels DAC DIGITAL VOLUME CONTROL The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 LDA[7:0] 11111111 (0dB) Digital Attenuation data for Left channel DACL in 0.5dB steps. See Table 11 01001 Digital Attenuation DACL 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store LDA in intermediate latch (no change to output) 1: Store LDA and update attenuation on all channels 7:0 RDA[6:0] 11111111 (0dB) Digital Attenuation data for Right channel DACR in 0.5dB steps. See Table 11 01010 Digital Attenuation DACR 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store RDA in intermediate latch (no change to output) 1: Store RDA and update attenuation on all channels. 7:0 ASTDA[7:0] 11111111 (0dB) Digital Attenuation data for both DAC channels in 0.5dB steps. See Table 11 10001 Master Digital Attenuation (both channels) 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels. |
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