MCP3461 datasheet(63/108 Pages) MICROCHIP

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DS20006180D-page 63

MCP3461/2/4

6.3

Writing to the Device

When the command type is “Incremental Write”

(CMD[1:0] = 10), the device enters Write mode and

starts writing the first data byte to the address given in

the CMD[5:2] bits.

After the STATUS byte has been transferred, SDO is

always in a High-Impedance state during an incremental

write communication. Writing to a read-only address

(such as addresses, 0x0 or 0xF) has no effect and does

not increment the Address Pointer. In this case, the

user needs to stop the communication and restart a

communication with a COMMAND byte pointing to a

writable address (0x1 to 0xD).

Each register is effectively written after receiving the

last bit for the register (SCK last rising edge). Any CS

rising edge during a write communication aborts the

current writing. In this case, the register being written

will not be updated and will keep its old value.

The registers may need 8, 16 or 24 bits to be effectively

written depending on their address (see Table 8-1). After

each register is written, the Address Pointer is automat-

ically incremented as long as CS stays logic low.

Attempted data writes to read-only registers will result in

the data byte being written to the next sequential writable

Pointer reaches 0xD, the next register to write is the reg-

ister 0x1 (see Figure 6-4 for a graphical representation

of the address looping). The incremental write feature

can be used to fully configure the part by using a unique

communication, which can save time in the application.

This unique communication can end at address 0xD so

that the user can also lock the configuration when

written, providing additional security in the application

(see Section 6.6 “Locking/Unlocking Register Map

Write Access”).

Internal registers, located at addresses 0xB, 0xC and

0xE, should be kept to their default state at all times for

proper operation. These are reserved registers and

should not be modified.

Figure 6-5 and Figure 6-6 show an example of a write

communication in detail with a single register

incremental write communication.

FIGURE 6-4:

Incremental Write Loop.

CONFIG1 (0x2)

CONFIG2 (0x3)

CONFIG3 (0x4)

IRQ (0x5)

MUX (0x6)

SCAN (0x7)

TIMER (0x8)

OF FSETCAL (0x9)

GAINCAL (0xA)

Reserved (0xB)

Reserved (0xC)

LOCK (0xD)

Reserved (0xE)

CONFIG0 (0x1)

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