Pin #

Pin Name

I/O

Description

DS90C124 DESERIALIZER PIN DESCRIPTIONS

29

VSSOR1

GND

Digital Ground, LVTTL O/P Ground

20

VDDOR2

VDD

Digital Voltage supply, LVTTL O/P Power

19

VSSOR2

GND

Digital Ground, LVTTL O/P Ground

7

VDDOR3

VDD

Digital Voltage supply, LVTTL O/P Power

8

VSSOR3

GND

Digital Ground, LVTTL O/P Ground

41

RIN+

LVDS_I

Receiver LVDS true (+) INput

42

RIN−

LVDS_I

Receiver LVDS inverted (−) INput

2

RESRVD

CMOS_I

RESERVED - tie Low

43

RRFB

CMOS_I

Receiver Rising Falling Bar clock Edge Select

RRFB = H; ROUT LVTTL O/P clocked on Rising CLK

RRFB = L; ROUT LVTTL O/P clocked on Falling CLK

48

REN

CMOS_I

Receiver ENable, (ACTIVE H)

REN = L; Disabled, ROUT[23-0] and RCLK TRI-STATED, PLL still operational

REN=H; Enabled

1

RPWDNB

CMOS_I

Receiver PoWer DowNBar (ACTIVE L)

RPWDNB = L; Disabled, ROUT[23-0], RCLK, and LOCK are TRI-STATED in stand-by

mode, PLL is shutdown

RPWDNB = H; Enabled

17

LOCK

CMOS_O

LOCK indicates the status of the receiver PLL

LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED

LOCK = H; receiver PLL is locked

25-28,

31-34

ROUT[7:0]

CMOS_O

Receiver Outputs – Group 1

13-16,

21-24

ROUT[15:8]

CMOS_O

Receiver Outputs – Group 2

3-6,

9-12

ROUT[23:16]

CMOS_O

Receiver Outputs – Group 3

18

RCLK

CMOS_O

Recovered CLocK. Parallel data rate clock recovered from the embedded clock.

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14