ACE24AC512EDPTH datasheet(5/18 Pages) ACE

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ACE24AC512E

Two-wire Serial EEPROM

VER 1.1

Figure 2: Timing diagram for output acknowledge

Device Addressing

The 2-wire serial bus protocol mandates an 8 bits device address word after a start bit condition to invoke

a valid read or write command. The first four most significant bits of the device address must be 1010,

which is common to all serial EEPROM devices. The next three bits are device address bits. These three

device address bits (5th, 6th and 7th) are to match with the external chip select/address pin states. If a

match is made, the EEPROM device outputs an acknowledge signal after the 8th read/write bit, otherwise

the chip will go into standby mode. However, matching may not be needed for some or all device address

bits (5th, 6thand 7th) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at VIH then

the chip goes into read mode. If a “0” is detected, the device enters programming mode.

ACE24AC512EDPTH Datasheet(PDF) 5 Page - ACE Technology Co., LTD.