SC4905AMSTR datasheet(12/20 Pages) SEMTECH

12 / 20 page

SC4905A/B

POWER MANAGEMENT

PRELIMINARY

 2002 Semtech Corp.

www.semtech.com

7) If an opto isolator is used for isolation, quiet primary

and secondary ground planes should be used. Same

precautions should be followed for the primary GND plane

as mentioned in item 5 mentioned above. For the sec-

ondary GND plane, the GND plane method mentioned

in item 4 should be followed.

8) All the noise sensitive components such as VFF, DMAX

resistive divider, reference by pass capacitor, VDD bypass

capacitor, current sensing circuitry, feedback circuitry, and

the oscillator resistor/capacitor network should be con-

nected as close as possible to the SC4905. The GND

return should be connected to the quiet SC4905 GND

plane.

9) The connection from the OUT of the SC4905 should be

minimized to avoid any stary inductance. If the layout can

not be optomized due to constraints, a small Schottky

diode maybe connected from the OUT pin to the ground

directly at the IC. This will clamp excessive negative volt-

ages at the IC. If drivers are used, the Schottky diodes

should be connected directly at the IC, from the output of

the driver to the driver ground.

10) If the SYNC function is not used, the SYNC pin should

be grounded at the SC4905 GND to avoid noise pick up.

Application Information (Cont.)

LAYOUT GUIDELINES

Careful attention to layout requirements are necessary for

successful implementation of the SC4905 PWM control-

ler.

High currents switching are present in the application

and their effect on ground plane voltage differentials must

be understood and minimized.

1). The high power parts of the circuit should be laid out

first. A ground plane should be used. The number and

position of ground plane interruptions should be such as

to not unnecessarily compromise ground plane integrity.

Isolated or semi-isolated areas of the ground plane may

be deliberately introduced to constrain ground currents to

particular areas, for example the input capacitor and FET

ground.

2). The loop formed by the Input Capacitor(s) (Cin), the

FET must be kept as small as possible. This loop contains

all the high current, fast transition switching. Connections

should be as wide and as short as possible to minimize

loop inductance. Minimizing this loop area will a) reduce

EMI, b) lower ground injection currents, resulting in electri-

cally cleaner grounds for the rest of the system and c)

minimize source ringing, resulting in more reliable gate

switching signals.

3). The connection between FETs and the Transformer

should be a wide trace or copper region. It should be as

short as practical. Since this connection has fast voltage

transitions, keeping this connection short will minimize EMI.

4) The output capacitor(s) (Cout) should be located as

close to the load as possible. Fast transient load cur-

rents are supplied by Cout only. Connections between

Cout and the load must be short, wide copper areas to

minimize inductance and resistance.

5) The SC4905 is best placed over a quiet ground plane

area. Avoid pulse currents in the Cin FET loop flowing in

this area. GND should be returned to the ground plane

close to the package and close to the ground side of (one

of) the VDD supply capacitor(s). Under no circumstances

should GND be returned to a ground inside the Cin and

FET loop. This can be achieved by making a star connec-

tion between the quiet GND planes that the SC4905 will

be connected to and the noisy high current GND planes

connected to the FETs.

6) The feed back connection between the error amplifier

and the FB pin should be kept as short as possible, and

the GND connections should be to the quiet GND used for

the SC4905.

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