MCP33151D-05T-ESLASHMS datasheet(6/66 Pages) MICROCHIP

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MCP33151D/41D-XX

DS20006219A-page 6

 2019 Microchip Technology Inc.

Spurious Free Dynamic Range

SFDR

MCP33151D-10 and MCP33151D-05: 14-bit ADC

—

110.5

—

dBc

VREF =5V, fIN =1 kHz

—

107.2

—

VREF =1.8V, fIN =1 kHz

—

105.9

—

VREF =5V, fIN =10kHz

—96.3

—

VREF =1.8V, fIN =10kHz

MCP33141D-10 and MCP33141D-05: 12-bit ADC

—

99.8

—

dBc

VREF =5V, fIN =1 kHz

—99.4

—

VREF =1.8V, fIN =1 kHz

—99.9

—

VREF =5V, fIN =10kHz

—95.2

—

VREF =1.8V, fIN =10kHz

Total Harmonic Distortion

(first five harmonics)

THD

MCP33151D-10 and MCP33151D-05: 14-bit ADC

—

-105.0

—

dBc

VREF =5V, fIN =1 kHz

—

-105.2

—

VREF =1.8V, fIN =1 kHz

—

103.2

—

VREF =5V, fIN =10kHz

—95.2

—

VREF =1.8V, fIN =10kHz

MCP33141D-10 and MCP33141D-05: 12-bit ADC

—

-100.7

—

dBc

VREF =5V, fIN =1 kHz

—

-100.3

—

VREF =1.8V, fIN =1 kHz

—

-100.4

—

VREF =5V, fIN =10kHz

—-94.2

—

VREF =1.8V, fIN =10kHz

System Self-Calibration

Self-Calibration Time

tCAL

—400

550

Note 2

Number of SCLK Clocks for

Recalibrate Command

ReCalNSCLK

—

1024

—

clocks Includes clocks for data bits

Serial Interface Timing Information: See Serial Interface Timing Specifications

Digital Inputs/Outputs

High-level Input Voltage

VIH

0.7 × D

VIO

—DVIO +0.3

DVIO ≥ 2.3V

0.9 × D

VIO

DVIO <2.3V

Low-level Input Voltage

VIL

-0.3

—

0.3 × DVIO

VDVIO ≥ 2.3V

-0.3

0.2 × DVIO

DVIO <2.3V

Hysteresis of Schmitt Trigger

Inputs

VHYST

—0.2 ×

DVIO

—

All digital inputs

TABLE 1-1:

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD =1.8V, DVIO =3.3V, VREF =5V,

GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, CLOAD_SDO = 20 pF, +25°C is applied

for typical values.

MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.

MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Note 1:

This parameter is ensured by design and not 100% tested.

This parameter is ensured by characterization and not 100% tested.

Decoupling capacitor is recommended on the following pins:

(a) AVDD pin: 1 µF ceramic capacitor, (b) DVIO pin: 0.1 µF ceramic capacitor,

Differential Input Full-Scale Range (FSR) = 2 × VREF.

PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result.

ENOB = (SINAD - 1.76)/6.02.

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