TR3003 datasheet(10/12 Pages) RFM

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TR3003-070105

Name

Description

TXMOD

The transmitter RF output voltage is proportional to the input current to this pin. A series resistor is used to adjust the peak

transmitter output voltage. 1.5 dBm output power requires about 250 µA of input current. In the ASK mode, minimum out-

put power occurs when the modulation driver sinks about 10 µA of current from this pin. In the OOK mode, input signals

less than 220 mV completely turn the transmitter oscillator off. Internally, this pin appears to be a diode in series with a

small resistor. Peak transmitter output power PO for a 3 Vdc supply voltage is approximately:

PO = 24*(ITXM)

2, where P

O is in mW, and the peak modulation current ITXM is in mA

A ±5% resistor value is recommended. In the OOK mode, this pin is usually driven with a logic-level data input (unshaped

data pulses). OOK modulation is practical for data pulses of 30 µs or longer. In the ASK mode, this pin accepts analog

modulation (shaped or unshaped data pulses). ASK modulation is practical for data pulses 8.7 µs or longer. The resistor

driving this pin must be low in the receive and power-down (sleep) modes. Please refer to the ASH Transceiver Designer’s

Guide for additional information on modulation techniques.

LPFADJ

This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor RLPF between this pin and

ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth fLPF from 4.5 kHz to 1.8

MHz. The resistor value is determined by:

RLPF = 1445/ fLPF, where RLPF is in kilohms, and fLPF is in kHz

A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between fLPF and 1.3*

fLPF with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase

response. The peak drive current available from RXDATA increases in proportion to the filter bandwidth setting.

GND2

GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.

RREF

RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1%

resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less

than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less

that 1.5 K, their node capacitance must be added to the RREF node capacitance and the total should not exceed 5 pF.

THLD2

THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set by a 0 to 200 K resistor RTH2

between this pin and RREF. Increasing the value of the resistor decreases the threshold below the peak detector value

(increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB below peak, or 60 mV

for a 50%-50% RF amplifier duty cycle. The value of the THLD2 resistor is given by:

RTH2 = 1.67*V, where RTH2 is in kilohms and the threshold V is in mV

A ±1% resistor tolerance is recommended for the THLD2 resistor. Leaving the THLD2 pin open disables the dB-below-

peak data slicer operation.

THLD1

The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor RTH1 to RREF. The threshold is

increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold. The value of the

resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the acceptable range for the resistor is

0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by:

RTH1 = 1.11*V, where RTH1 is in kilohms and the threshold V is in mV

For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 200 K, again providing a THLD1

range of 0 to 90 mV. The resistor value is given by:

RTH1 = 2.22*V, where RTH1 is in kilohms and the threshold V is in mV

A ±1% resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required for

proper AGC operation.

PRATE

The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to

the first RF amplifier tPRI is set by a resistor RPR between this pin and ground. The interval tPRI can be adjusted between

0.1 and 5 µs with a resistor in the range of 51 K to 2000 K. The value of RPR is given by:

RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms

A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifi-

ers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period tPRC from start-

to-start of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resis-

tor of 11 K to 220 K. In this case the value of RPR is given by:

RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms

A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for additional

amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and this pin to less than

5 pF to maintain stability.

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