AX88141 datasheet(10/43 Pages) ASIX

10 / 43 page

AX88141

PRELIMINARY

ASIX ELECTRONICS CORPORATION

CONFIDENTIAL

2.0 Signal Description

2.1 Signal Descriptions

The following terms describe the AX88141 pin-out:

Address phase

Address and appropriate bus commands are driven during this cycle.

Data phase

Data and the appropriate byte enable codes are driven during this cycle.

All pin names with the # suffix are asserted low.

The following abbreviations are used in Tab - 1 PCI interface group Tab - 2 Boot ROM , Serial ROM , General-

purpose signals group

,Tab - 3 MII interface signals group ,Tab - 4 Power pins group..

Input

Output

I/O

Input /Output

O/D

Open Drain

2.2 PCI interface group

SIGNAL

TYPE

NUMBER

DESCRIPTION

CBE#<3>

CBE#<2>

CBE#<1>

CBE#<0>

I/O

21,

38,

48,

BUS COMMAND and BYTE ENABLE Are multiplexed on the same PCI pins. During the address

phase of the transaction, CBE#<3:0> Provide the BUS COMMAND. During the data phase,

CBE#<3:0> Provide the BYTE ENABLE. The BYTE ENABLE determines which byte lines carry

valid data., CBE#<0> Applies to byte 0, and CBE#<3> Applies to byte 3.

DEVSEL#

I/O

Device select Is asserted by the target of the current bus access. When the AX88141 is the master of the

current bus access, the target assert DEVSEL# confirming the access. It is driven by AX88141 When

AX88141 is selected as a slave.

FRAME#

I/O

The FRAME# Signal is driven by the AX88141 To indicate the beginning and duration of an access.

FRAME# Asserts to indicate the beginning of a bus transaction. While FRAME# is asserted, data

transfers continue. When FRAME# deasserts the next data phase is the final data phase transaction.

GNT#

BUS GRANT Indicates to the AX88141 That access to the bus is granted.

IDSEL

Initialization devise select asserts To indicate that the host is issuing a configuration cycle to the

AX88141.

INT#

O/D

Interrupt request asserts When one of the appropriate bits of reg5 sets and causes an interrupt, provided

that the corresponding mask bit in reg7 is not asserted. interrupt request deasserts by writing a 1 into the

appropriate reg5 bit.

This pin must be pulled up by an external resistor.

IRDY#

I/O

Initiator ready Indicates the bus master

ability to complete the current data phase of the transaction.

A data phase is completed on any rising edge of the clock When both IRDY# and target ready TRDY#

are asserted. Wait cycles are inserted until both IRDY# and TRDY# are asserted together.

When the AX88141 is the bus master, IRDY# is asserted during write operations to indicate that valid

data is present on the AD<31:0>. During read operations, the AX88141 asserts IRDY# to indicate that

it is ready to accept data.

PAR

I/O

Parity is an even parity bit for the AD<31:0> AD and CBE#<3:0>.

During address and data phases, parity is calculated on all the AD<31:0> AND CBE#<3:0>lines

whether or not any of these lines carry meaningful information.

AX88141 Datasheet(PDF) 10 Page - ASIX Electronics Corporation

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