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Digital Outputs

THS1215

DA11

DA0

SN74ALVCH16841

12

1D9

1D0

2D7

2D2

LE

OE

1Q9

1Q0

2Q9

2Q2

12

ASIC

or

DSP

2D1

2D0

2Q1

2Q0

FIFO

D11

D0

1Q15

1Q0

16

DSP

WRTCLK

HF flag

INTR

D15

D12

THS1215

DA11

DA0

12

15 MHz

Clock

CLK

Layout, Decoupling, and Grounding Rules

THS1215

SLAS292A – MARCH 2001 – REVISED MARCH 2004

The output of THS1215 is in unsigned binary code. The ADC input over-range indicator is output on pin OVRNG.

Capacitive loading on the output should be kept as low as possible (a maximum loading of 10 pF is

recommended) to ensure best performance. Higher output loading causes higher dynamic output currents and

can therefore increase noise coupling into the part's analog front-end. To drive higher loads, the use of an output

buffer is recommended.

When clocking output data from THS1215, it is important to observe its timing relation to CLK. The pipeline ADC

delay is 5 clock cycles to which the maximum output propagation delay needs to be added.

Figure 20. Buffered Output Connection

Figure 21. FIFO Connection

Proper grounding and layout of the PCB on which THS1215 is populated is essential to achieve the stated

performance. It is advised to use separate analog and digital ground planes that are spliced underneath the IC.

THS1215 has digital and analog pins on opposite sides of the package to make this easier. Because there is no

connection internally between analog and digital grounds, they have to be joined on the PCB. It is advised to do

this at one point in close proximity to THS1215.

Because of the high sampling rate and switched-capacitor architecture, THS1215 generates transients on the

supply and reference lines. Proper decoupling of these lines is therefore essential. EVM decoupling is

recommended as shown in Figure 22.

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