M440T513Y datasheet(16/26 Pages) STMICROELECTRONICS

16 / 26 page

M440T513Y

16/26

Command Register

Address location 0Bh is the Command Register

where mask bits, control bits, and flag bits reside.

The operation of each bit is as follows:

TE - Bit 7 Transfer Enable. This bit, when set to

logic '0,' will disable the transfer of data between

internal and external clock registers. The contents

in the external clock registers are now frozen and

READs or WRITEs will not be affected with up-

dates. This bit must be set to a logic '1' to allow up-

dates.

IPSW - Bit 6 Interrupt Switch. When set to a

logic '1,' IRQ/(IRQ) is the Watchdog Alarm. When

set to a logic '0,' IRQ/(IRQ) is the time of day alarm

output.

IBH/LO - Bit 5 IRQ Sink or Source Current.

When this bit is set to a logic '1' and VCC is applied,

IRQ/(IRQ)

will

source

current

(see

Table

11., page 19, IOH). When this bit is set to a logic '0,'

IRQ will sink current (see Table 11., page 19, IOL).

PU/LVL - Bit 4 Interrupt Pulse Mode or Level

Mode. This bit determines whether the interrupt

will output a pulse or level signal. When set to a

logic '0,' IRQ/(IRQ) will be in the level mode. When

this bit is set to a logic '1,' the pulse mode is select-

ed. IRQ/(IRQ) will either sink or source current, de-

pending on the condition of Bit 5, for a minimum of

3ms and then release. IRQ will only source current

when there is voltage present on VCC.

WAM - Bit 3 Watchdog Alarm Mask. When this

bit is set to a logic '0,' the watchdog interrupt output

will be activated. The activated state is determined

by bits 1, 4, 5, and 6 of the Command Register.

when this bit is set to a logic '1,' the watchdog in-

terrupt output is deactivated.

TDM - Bit 2 Time of Day Alarm Mask. When

this bit is set to a logic '0,' the time of day alarm in-

terrupt output will be activated. The activated state

is determined by bits 0, 4, 5, and 6 of the Com-

mand Register. When this bit is set to a logic '1,'

the time of day alarm interrupt output is deactivat-

ed.

WAF - Bit 1 Watchdog Alarm Flag. This bit is

set to a logic '1' when a watchdog alarm interrupt

occurs. This bit is “Read only.” The bit is reset

when any of the watchdog alarm registers are ac-

cessed.

When the interrupt is in the pulse mode (see PU/

LVL - Bit 4 Interrupt Pulse Mode or Level Mode),

this flag will be in the logic '1' state only during the

time the interrupt is active.

TDF - Bit 0 Time of Day Flag. This is a “Read

only” bit. This bit is set to a logic '1' when a time of

day alarm has occurred. the time the alarm oc-

curred can be determined by reading the time of

day alarm registers. This bit is reset to a logic '0'

state when any of the time of day registers are ac-

cessed.

When the interrupt is in the pulse mode (see PU/

LVL - Bit 4 Interrupt Pulse Mode or Level Mode),

this flag will be in the logic '1' state only during the

time the interrupt is active.

Battery Low

The M440T513Y automatically performs battery

voltage monitoring upon power-up, and at factory-

programmed time intervals of at least 24 hours.

The Battery Low (BL) signal will be asserted if the

battery voltage is found to be less than approxi-

mately 2.5V. The BL signal will remain asserted

until completion of battery replacement and sub-

sequent battery low monitoring tests, either during

the next power-up sequence or the next scheduled

24-hour interval (see application note, “AN1540,

NVRAM PBGA Dual Battery Hat Mounting and

Removal” for more information).

If a battery low is generated during a power-up se-

quence, this indicates that the battery is below

2.5V and may not be able to maintain data integrity

in the SRAM. Data should be considered suspect,

and verified as correct. Fresh batteries should be

installed.

If a battery low indication is generated during the

24-hour interval check, this indicates that one of

the batteries is near end of life. However, data is

not compromised due to the fact that a nominal

VCC is supplied. In order to insure data integrity

during subsequent periods of battery back-up

mode, the batteries should be replaced. The

SNAPHAT® top should be replaced with valid VCC

applied to the device.

The M440T513Y only monitors the batteries when

a nominal VCC is applied to the device. Thus appli-

cations which require extensive durations in the

battery back-up mode should be powered-up peri-

odically (at least once every few months) in order

for this technique to be beneficial. Additionally, if a

battery low is indicated, data integrity should be

verified upon power-up via a checksum or other

technique. The BL signal is an open drain output

and an appropriate pull-up resistor should be cho-

sen to control the rise time.

Sleep Mode

Forcing the sleep pad more positive than +7.5V

above ground will cause the batteries to be isolat-

ed from the RAM, preserving the remaining battery

life. This mode may be used when device opera-

tion is not necessary for an extended period of

time.

Note: Implementation of this Sleep Mode will re-

sult in complete loss of data.

M440T513Y Datasheet(PDF) 16 Page - STMicroelectronics

M440T513Y Datasheet(HTML) 16 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL