THS1007

SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

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5

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AINP

32

I

Analog input, single-ended or positive input of differential channel A

AINM

31

I

Analog input, single-ended or negative input of differential channel A

BINP

30

I

Analog input, single-ended or positive input of differential channel B

BINM

29

I

Analog input, single-ended or negative input of differential channel B

AVDD

23

I

Analog supply voltage

AGND

24

I

Analog ground

BVDD

7

I

Digital supply voltage for buffer

BGND

8

I

Digital ground for buffer

CONV_CLK

15

I

Digital input. This input is the conversion clock input.

CS0

22

I

Chip select input (active low)

CS1

21

I

Chip select input (active high)

SYNC

16

O

Synchronization output. This signal indicates in a multichannel operation that data of channel A is brought to

the digital output and can therefore be used for synchronization.

DGND

17

I

Digital ground. Ground reference for digital circuitry.

DVDD

18

I

Digital supply voltage

D0 – D9

1–6,

9–12

I/O/Z

Digital input, output; D0 = LSB

RA0

13

I

Digital input. RA0 is used as an address line for the control register. This is required for writing to the control

register 0 and control register 1. See Table 7.

RA1

14

I

Digital input. RA1 is used as an address line for the control register. This is required for writing to control

register 0 and control register 1. See Table 7.

REFIN

28

I

Common-modereference input for the analog input channels. It is recommended that this pin be connected to

the reference output REFOUT.

REFP

26

I

Reference input, requires a bypass capacitor of 10

µF to AGND in order to bypass the internal reference

voltage. An external reference voltage at this input can be applied. This option can be programmed through

control register 0. See Table 8.

REFM

25

I

Reference input, requires a bypass capacitor of 10

µF to AGND in order to bypass the internal reference

voltage. An external reference voltage at this input can be applied. This option can be programmed through

control register 0. See Table 8.

REFOUT

27

O

Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250

µA. The reference output

requires a capacitor of 10

µF to AGND for filtering and stability.

RD(1)

19

I

The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input,

active low as a data read select from the processor. See timing section.

WR (R/W)(1)

20

I

This input is programmable. It functions as a read-write input R/W and can also be configured as a write-only

input WR, which is active low and used as data write select from the processor. In this case, the RD input is

used as a read input from the processor. See timing section.

(1) The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.