THS1007

SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

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16

Conversion

During conversion, the ADC operates with a free running external clock applied to the input CONV_CLK. With

every falling edge of the CONV_CLK signal a new converted value is available to the data bus with the

corresponding read signal. The THS1007 allows up to four analog inputs to be selected. The inputs can be

configured as two differential channels, four single-ended channels or a combination of differential and

signle-ended.

To provide the system with channel information, the THS1007 utilizes an active low SYNC signal. When

operated in a multichannel configuration, the SYNC signal is active low when data from channel 1 is available

to the databus. When operated in signle-channel mode (single-ended or differential operation) the SYNC signal

is disabled.

Figure 28 shows the timing of the conversion, when one analog input channel is selected. The maximum

throughput rate is 6 MSPS in this mode. The signal SYNC is disabled for the selection of one analog input since

this information is not necessary. There is a certain timing relationship required for the read signal with respect

to the conversion clock. This can be seen in Figure 28 and the timing specifications. A more detailed description

of the timing is given in the timing section and signal description of the THS1007.

Sample N

Channel 1

Sample N+2

Channel 1

Sample N+3

Channel 1

Sample N+1

Channel 1

Sample N+4

Channel 1

Sample N+5

Channel 1

Sample N+6

Channel 1

Data N–1

Channel 1

Data N

Channel 1

Data N+1

Channel 1

Data N+2

Channel 1

Data N–4

Channel 1

Data N–3

Channel 1

Data N–2

Channel 1

AIN

CONV_CLK

READ†

†READ is the logical combination from CS0, CS1 and RD

td(A)

td(pipe)

tw(CONV_CLKH)

tw(CONV_CLKL)

tc

tsu(CONV_CLKL-READL)

tsu(READH-CONV_CLKL)

Figure 28. Conversion Timing in 1-Channel Operation

Figure 29 shows the conversion timing when two analog input channels are selected. The maximum throughput

rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted

data is available to the data bus. The SYNC pulse is active low when the data of channel one is available to

the databus. The data of channel one is followed by the data of channel two before the SYNC signal is active

low again.