73S8024C Data Sheet

DS_8024C_023

10

Rev. 1.3

The following steps and Figure 4 show the activation sequence and the timing of the card control signals

when the system controller pulls

CMDVCC low while RSTIN is high:

1.

CMDVCC is set low.

2.

3.

After the fall of RSTIN at t

power to the card is shut down.

2

4.

CLK is applied to the card at the end of t

, turn I/O (AUX1, AUX2) to reception mode.

3

5.

RST is a copy of RSTIN after t

after I/O is in reception mode.

set RST high until 42,000 clock cycles after the start of CLK.

Figure 4: Activation Sequence – RSTIN high when

CMDVCC goes low

9

Deactivation Sequence

Deactivation is initiated either by the system controller by setting the

CMDVCC high, or automatically in

The following steps and

fault, and card

extraction during the session.

Figure 5 show the deactivation sequence and the timing of the card control signals

when the system controller sets the

CMDVCC high or OFF goes low due to a fault or card removal:

1.

2.

CLK is set low at the end of time t

.

2

3.

I/O goes low at the end of time t

.

3

4.

V

. Out of reception mode.

≥ 0.5 µs, CLK active

≥ 42000 card clock cycles (time for RST to become the copy of RSTIN).

CMDVCC

VCC

IO

CLK

RSTIN

RST