PLL102-108

Programmable DDR Zero Delay Clock Driver

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 03/29/02 Page 2

PIN DESCRIPTIONS

Name

Number

Type

Description

VDD

4,11,15,21,28,34,

38,45

P

2.5V power supply.

GND

1,7,8,18,24,

25,31,41,42,48

P

Ground

AVDD

16

P

Analog power supply (2.5V).

AGND

17

P

Analog ground.

CLKT(0:9)

3,5,10,20,22,46,

44,39,29,27

I

“True” clocks of differential pair outputs.

CLKC(0:9)

2,6,9,19,23,47,

43,40,30,26

I

“Complementary” clocks of differential pair outputs.

CLK_INT

13

I

Single-ended 3.3V tolerant input.

N/C

14,32,36

Not connected.

FB_OUTT

33

O

“True” feedback output. Dedicated for external feedback. It switches at the

same frequency as the CLK_INT.

FB_INT

35

I

“True” feedback input, provides feedback signal to the internal PLL for

synchronization with CLK_INT to eliminate phase error.

SDATA

37

B

SCLK

12

I

Serial data input for serial interface port.

Functionality

INPUTS

OUTPUTS

AVDD

CLK_INT

CLK_INC

CLKT

CLKC

FB_OUTT

PLL State

2.5V (Nom)

L

H

L

H

L

On

2.5V (Nom)

H

L

H

L

H

On

GND

L

H

L

H

L

Bypass/Off

GND

H

L

H

L

H

Bypass/Off