Preliminary

PLL103-07

2 DIMM DDR Fanout Buffer

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 01/03/01 Page 6

3. Electrical Specifications (Continued)

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Supply Current

(DDR-only mode)

Unloaded outputs, 133MHz

TBM

mA

Supply Current

(SDRAM mode)

Unloaded outputs, 133MHz

TBM

mA

Supply Current

PD = 0

TBM

mA

Output Crossing

Voltage

(VDD/2)

-0.1

VDD/2

(VDD/2)+

0.1

V

Output Voltage Swing

0.7

VDD-0.4

V

Duty Cycle

Measured @ 1.5V

45

50

55

%

Max. Operating

Frequency

66

170

MHz

Rising Edge Rate

Measured @

0.4V ~ 2.4V

1.0

1.5

2.0

V/ns

Falling Edge Rate

Measured @

2.4V ~ 0.4V

1.0

1.5

2.0

V/ns

DDR Rising Edge Rate

Measured between 20% to 80% of

output

0.25

0.6

1.0

V/ns

DDR Falling Edge Rate

Measured between 20% to 80% of

output

0.25

0.6

1.0

V/ns

Clock Skew(pin to pin)

All outputs equally loaded

100

ps

Stabilization Time

0.1

ms

Note: TBM: To be measured