2.

Periphery

2.1

Buffer Descriptions

The peripheral I/O buffer is the electrical interface between the external signals (voltage range from 2.3V to 3.6V and

from 4.5V to 5.5V) and the internal core signals (from 1.65V to 1.95V).

I/O libraries are:

• IO5V0 I/O – Powered at 5V

• IO3V3 I/O – Powered at 3.3V

• IO2V5 I/O – Powered at 2.5V, 3.3V tolerant

All I/O buffers are cold sparing and include:

• Bidirectional I/O buffers

• Tristate-output I/O buffers

• Output-only I/O buffers

• Input-only I/O buffers (inverting, non-inverting, Schmitt trigger)

Furthermore, the bidirectional, tristate-output and input-only I/O buffers are available with or without pull-up or

pull-down structures.

Specific I/O buffers have been developed in 3.3V and 2.5V:

• LVDS transmitter and receiver differential I/O buffers.

• LVPECL receiver differential I/O buffers

• In 3.3V, PCI-compliant output buffer

I/O buffers are tolerant, that is, the pad signal can be higher than VCCB when it is high impedance (input or

bidirectional buffers, tristate buffers in HiZ and LVDS when disable).

I/O buffers are cold sparing, that is, the pad signal can be applied when VCCB is 0V. In both cases, tolerant or

cold sparing, there is no impact on core supply, buffer supply, and reliability, if the applied signal respects the

recommended operating conditions, and the leakage current is less than 1µA.

2.2

I/O Clusters

The periphery of the chip (pad ring) can be split into several I/O segments (I/O clusters). Some clusters can be

unpowered while others are active.

A specific power control line is distributed inside the cluster to force all the I/Os of the cluster in tristate mode

regardless of their initial state (i.e., an output-only buffer will also be turned to HiZ mode).

2.3

Double Pad Ring

In case of a large number of IOs, Microchip can provide a double pad ring configuration, where the inner ring is used

exclusively for core power supply pads.

ATMX150RHA

Periphery

Datasheet

DS60001543C-page 5