Preliminary

PLL520-88/-89

Low Phase Noise VCXO (9.5-65MHz)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1

FEATURES

• 19MHz to 65MHz fundamental crystal input.

• Output range: 9.5MHz – 65MHz

• Complementary outputs: PECL or LVDS output.

• Selectable OE Logic (enable high or enable low).

• Integrated variable capacitors.

• Supports 2.5V or 3.3V Power Supply.

• Available in 16 pin TSSOP package.

DESCRIPTION

The PLL520-88 (PECL) and PLL520-89 (LVDS) are

VCXO ICs specifically designed to work with

fundamental crystals between 19MHz and 65MHz.

The selectable divide by two feature extends the

operation range from 9.5MHz to 65MHz. They

require very low current into the crystal resulting in

better overall stability. The OE logic feature allows

selection of enable high or enable low.

BLOCK DIAGRAM

PIN CONFIGURATION

OUTPUT SELECTION AND ENABLE

OE_SELECT

OE_CTRL

State

0

Tri-state

0

1 (Default)

Output enabled

0 (Default)

Output enabled

1 (Default)

1

Tri-state

Input selection: Bond to GND to set to “0”, bond to VDD to set to “1”

No connection results to “default” setting through

internal pull-up/-down.

OE_CTRL:

Logical states defined by PECL levels if

OE_SELECT is “1”

Logical states defined by CMOS levels if

OE_SELECT is “0”

OUTPUT FREQUENCY DIVIDE BY

TWO SELECTOR

S2

Output

0

Intput/2

1

Input

O

Q

PLL520-8X Block Diagram

Q

Oscillator

Amplifier

with

Integrated

Varicaps

S2

VCON

X+

X-

1

2

3

4

5

6

7

8

VDD

9

10

11

12

13

14

15

16

XIN

XOUT

DNC

S2

OE

VCON

GND

DNC

DNC

GNDBUF

QBAR

VDDBUF

Q

GNDBUF

GND