AT45DB321E datasheet(53/70 Pages) DIALOG

53 / 70 page

AT45DB321E

8784L–DFLASH–3/2019

21.

AC Waveforms

Four different timing waveforms are shown in Figure 21-1 through Figure 21-4. Waveform 1 shows the SCK signal being

low when CS makes a high-to-low transition and Waveform 2 shows the SCK signal being high when CS makes a

high-to-low transition. In both cases, output SO becomes valid while the SCK signal is still low (SCK low time is specified

as t

WL). Timing Waveforms 1 and 2 conform to RapidS serial interface but for frequencies up to 85MHz. Waveforms 1

and 2 are compatible with SPI Mode 0 and SPI Mode 3, respectively.

Waveform 3 and 4 illustrate general timing diagram for RapidS serial interface. These are similar to Waveform 1 and 2,

except that output SO is not restricted to become valid during the tWL period. These timing waveforms are valid over the

full frequency range (maximum frequency = 85MHz) of the RapidS serial case.

Figure 21-1. Waveform 1 = SPI Mode 0 Compatible

Figure 21-2. Waveform 2 = SPI Mode 3 Compatible

SCK

tCSS

Valid In

tSU

tWH

tWL

tCSH

tCS

High-impedance

Valid Out

tHO

tDIS

High-impedance

SCK

tCSS

Valid In

tSU

tWL

tWH

tCSH

tCS

High Z

Valid Out

tHO

tDIS

High-impedance

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