PLL502-30

750kHz – 800MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 4

5. Jitter Specifications

PARAMETERS

CONDITIONS

FREQUENCY

MIN.

TYP.

MAX.

UNITS

19.44MHz

2.2

77.76MHz

3.5

155.52MHz

4.3

With capacitive decoupling

between VDD and GND.

Over 10,000 cycles.

622.08MHz

5.0

ps

19.44MHz

17

77.76MHz

25

155.52MHz

27

Period jitter Peak-to-

With capacitive decoupling

between VDD and GND.

Over 10,000 cycles.

622.08MHz

35

ps

155.52MHz

2.6

4

Integrated 12 kHz to 20 MHz

622.08MHz

2.5

4

ps

6. Phase Noise Specifications

PARAMETERS

FREQUENCY

@10Hz

@100Hz

@1kHz

@10kHz

@100kHz

UNITS

19.44MHz

-80

-108

-132

-142

-150

77.76MHz

-72

-103

-122

-130

-125

155.52MHz

-65

-95

-120

-125

-121

to carrier

(typical)

622.08MHz

-55

-85

-109

-115

-110

dBc/Hz

Note: Phase Noise measured at VCON = 0V

7. CMOS Electrical Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

30

mA

Output drive current

(High Drive)

30

mA

10

mA

Output drive current

(Standard Drive)

10

mA

Output Clock Rise/Fall Time

(Standard Drive)

0.3V ~ 3.0V with 15 pF load

2.4

Output Clock Rise/Fall Time

(High Drive)

0.3V ~ 3.0V with 15 pF load

1.2

ns