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PLL502-50DI Datasheet(PDF) 1 Page - PhaseLink Corporation

Part # PLL502-50DI
Description  VCXO IC Die for 20 to 52MHz Parallel Resonant Crystals
PDF  4 Pages
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Manufacturer  PLL [PhaseLink Corporation]
Direct Link  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PLL502-50DI Datasheet(HTML) 1 Page - PhaseLink Corporation

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PLL502-50
VCXO IC Die for 20 to 52MHz Parallel Resonant Crystals
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 1
FEATURES
• Integrated voltage-controlled crystal oscillator
circuitry (VCXO) (pull range 380ppm minimum).
• Selectable frequency dividers (x1, 1/2, 1/4, 1/8)
available as bonding options.
• VCXO tuning range: 0.3V - 3.0V.
• Uses inexpensive fundamental-mode parallel
resonant crystals (from 20 to 52MHz).
• 2.5V or 3.3V supply voltage.
• Selectable High Drive (30mA) or Standard Drive
(10mA) CMOS output.
• Available in DIE (65 mil x 62 mil).
DESCRIPTION
The PLL502-50 is a monolithic low jitter, high
performance CMOS VCXO IC Die. It allows the
control of the output frequency with an input voltage
(VCON), using a low cost crystal.
The same die can be used as a VCXO with output
frequencies ranging from FXIN x 1 to FXIN / 8 thanks
to selector pads allowing bonding options (see
Divider Selection Table on this page). This makes
the PLL502-50 ideal for a wide range of applications
from 2.5MHz to 52MHz (including 27MHz,
35.328MHz, etc.).
BLOCK DIAGRAM
DIE SPECIFICATIONS
Name
Value
Size
62 x 65 mil
Reverse side
GND
Pad dimensions
80 micron x 80 micron
Thickness
10 mil
DIE CONFIGURATION
DIVIDER SELECTION
SELECTION
S2
S1
S0
FXIN
CLK (MHz)
0
0
0
FXIN x 1
0
0
1
FXIN
÷ 2
0
1
0
FXIN
÷ 4
0
1
1
FXIN x 1*
1
0
0
FXIN
÷ 8
1
0
1
FXIN
÷ 4*
1
1
0
FXIN
÷ 2*
1
1
1
20MHz – 52MHz
FXIN
÷ 8*
Note: Selector pads default to ‘0’, wire bond to VDD to set to ‘1’
(*) High-drive CMOS output
PAD DESCRIPTIONS
Name
Number
Description
XIN
27
Crystal input connection.
XOUT
29
Crystal output connection.
VCON
31
Voltage Control input.
GND
7,10
Ground.
CLK
13
Clock output.
S[0:2]
18,19,20
Frequency selection pad
VDD
21,22,23
Power supply.
OE
25
Output Enable: ‘0’ to disable
(tri-state output), 1’ (default
value when not connected) to
enabled the output.
VCON
XIN
VCXO
CLK
Selectable
Divider
18
19
20
21
23
25
7
13
10
27
29
31
Y
X
(0,0)
(1550,1475)
65 mil
GND
CLK
VCON
XOUT
XIN
Note:
^ denotes internal pull up
V denotes internal pull down
Die ID:
A0303-03J
C502A


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