SLG46855 datasheet(92/200 Pages) DIALOG

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Datasheet

23-Jul-2021

CFR0011-120-00

Revision 3.15

92 of 200

SLG46855

GreenPAK Programmable Mixed-Signal Matrix

Analog Comparators

There are two High Speed and two Low Power Rail-to-Rail General Purpose Analog Comparators (ACMP) macrocells in the

SLG46855. In order for the ACMP cells to be used in a GreenPAK design, the power up signals (ACMP0H PWR UP, ACMP1H

PWR UP, ACMP2L PWR UP, and ACMP3L PWR UP) need to be active. By connecting to signals coming from the Connection

Matrix, it is possible to have each ACMP be ON continuously, OFF continuously, or switched on periodically based on a digital

signal coming from the Connection Matrix. When ACMP is powered down, its output is low.

Two of the four General Purpose Analog Comparators are optimized for high speed operation (ACMP0H and ACMP1H), and two

other are optimized for low power operation (ACMP2L and ACMP3L).

Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources, and can also have a

selectable gain stage (1x, 0.5x, 0.33x, 0.25x) before connection to the analog comparator. The gain divider is unbuffered and has

input resistance of 2 M

Ω (typ) for 0.5x, 0.33x, 0.25x, and 10 GΩ for 1x. Each of the ACMP cells has a negative input signal that

is either created from an internal Vref or provided by any external source (GPIO2 and GPO0). Note that the external Vref signal

is filtered with a 2nd order low pass filter with 8 kHz typical bandwidth, see Figure 62 to Figure 65.

Input bias current < 1 nA (typ).

PWR UP = 1 => ACMP is powered up.

PWR UP = 0 => ACMP is powered down.

During power-up, the ACMP output will remain LOW, and then becomes valid in 52 μs (max) after power up signal goes high for

ACMP0H and ACMP1H, and becomes valid 325 μs (max) after power up signal goes high for ACMP2L and ACMP3L.

Each High Speed ACMP (ACMP0H and ACMP1H) has an optional Rail-to-Rail Input Buffer, which can be used along with the

Gain divider to increase ACMP input resistance. However, Input buffer will increase an input offset voltage.

Each cell also has a hysteresis selection, to offer hysteresis of (0, 32, 64, 192) mV. The hysteresis option is available when using

an internal Vref only.

The ACMP0H has an additional option of connecting an internal 100 μA current source to its positive input, register [690]. It is

also possible to connect the 100 μA current source to each next ACMP via an internal analog MUX.

ACMP0H IN+ options are GPIO4, buffered GPIO4, VDD, 100 μA Current Source

ACMP1H IN+ options are GPIO5, buffered GPIO5, ACMP0H IN+ MUX output

ACMP2L IN+ options are GPIO6, ACMP0H IN+ MUX output, ACMP1H IN+ MUX output

ACMP3L IN+ options are GPIO7, ACMP2L IN+ MUX output, Temp Sensor OUT

SLG46855 Datasheet(PDF) 92 Page - Dialog Semiconductor