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DA9231 Datasheet(PDF) 37 Page - Dialog Semiconductor

Part # DA9231
Description  Ultra-Low Quiescent Current Buck and LDO
PDF  55 Pages
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Manufacturer  DIALOG [Dialog Semiconductor]
Direct Link  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

DA9231 Datasheet(HTML) 37 Page - Dialog Semiconductor

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DA9231
Ultra-Low Quiescent Current Buck and LDO
Datasheet
Revision 2.4
3-Sep-2018
CFR0011-120-00 Rev 5
37 of 55
© 2018 Dialog Semiconductor
10.6 I
2C Programing
10.6.1
Interface Description
DA9231 includes an I
2C compatible interface based on the following signals:
● SCL: standard 400 kHz I2C bus serial clock generated by the Host processor
● SDA: standard 400 kHz I2C bus serial address/data input output
SDA and SCL are open drain I/O terminals. The standard frequency of the I
2C bus is 400 kHz in fast
mode or 100 kHz in slow mode.
SCL
SDA
Serial Interface
I2C
Figure 54: I
2C Serial Interface Pins
The I
2C bus is used to control most functions and change register values depending on the
application requirements. In active battery, the I
2C circuitry is powered from the battery. The interface
maintains a proper operation as long as VDD_SYS is valid.
The device is compatible with the standard I
2C protocol but only operates as a slave. The transfer
protocol is the same whether operating in fast or slow mode.
10.6.2
Details of the I
2C Protocol
The device supports 7-bit addressing only, the address is 2F. The 8-bit shifted address is 5E.
A timer runs during I
2C transitions. If the timer expires while SDA is held low, all additional
commands are ignored and the I
2C state machine is reset. The timer is reset with a START condition
and stopped with a STOP condition.
The I
2C bus is monitored at all times for a valid SLAVE address, and an acknowledge bit is
generated if the SLAVE address was true.
● A START condition is initiated by a high to low transition on the SDA line while the SCL is in the
high state.
● A STOP condition is indicated by a low to high transition on the SDA line while the SCL is in the
high state.
● An ACKNOWLEDGE is indicated by the receiver pulling the SDA line low during the following
clock cycle.
SDA
SCL
Data SDA must be stable
during high part of clock
SCL
Data sampled on SCL
rising edge and driven on
SCL falling edge
Start ( S ) is SDA falling while
SCL high
Stop (P ) is SDA rising while
SCL high
Figure 55: I
2C Start and Stop Conditions



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