84324EM

www.icst.com/products/hiperclocks.html

REV. A SEPTEMBER 18, 2003

7

Integrated

Circuit

Systems, Inc.

ICS84324

PRELIMINARY

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS84324 provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 2 illustrates how

a 24

Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each V

24

Ω

V

CCA

10

µF

.01

µF

3.3V

.01

µF

V

CC

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

(V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs.Therefore, terminat-

ing resistors (DC current path to ground) or current sources

must be used for functionality. These outputs are designed to

drive 50

Ω transmission lines. Matched impedance techniques

should be used to maximize operating frequency and minimize

signal distortion.

Figures 3A and 3B show two different layouts

which are recommended only as guidelines. Other suitable clock

layouts may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.