ICS10001B21 datasheet(15/21 Pages) ICST

15 / 21 page

810001BK-21

www.icst.com/products/hiperclocks.html

REV. A AUGUST 12, 2005

Integrated

Circuit

Systems, Inc.

ICS810001-21

FEMTOCLOCKS™DUAL VCXO VIDEO PLL

PRELIMINARY

NOTES ON SETTING THE VALUE OF C

As another general rule, the following relationship should be

maintained between components C

S and CP in the loop filter:

P establishes a second pole in the VCXO PLL loop filter. For

higher damping factors (> 1), calculate the value of C

P based on

a C

S value that would be used for a damping factor of 1. This will

minimize baseband peaking and loop instability that can lead to

output jitter.

P also dampens VCXO PLL input voltage modulation by the

charge pump correction pulses. A C

P value that is too low will

result in increased output phase noise at the phase detector

frequency due to this. In extreme cases where input jitter is high,

charge pump current is high, and C

P is too small, the VCXO PLL

input voltage can hit the supply or ground rail resulting in non-

linear loop response.

The best way to set the value of C

P is to use the filter response

software available from ICS (please refer to the following section).

P should be increased in value until it just starts affecting the

passband peak.

NOTES ON EXTERNAL CRYSTAL LOAD CAPACITORS

In the loop filter schematic diagram, capacitors are shown be-

tween pins 27/30 to ground and between pins 38/31 to ground.

These are optional crystal load capacitors which can be used to

center tune the external pullable crystal (the crystal frequency

can only be lowered by adding capacitance, it cannot be raised).

Note that the addition of external load capacitors will decrease

the crystal pull range and the Kvco value.

LOOP FILTER RESPONSE SOFTWARE

Online tools to calculate loop filter response can be found at

www.icst.com. Contact your local sales representative if a tool

cannot be found for this product.

P =

EXTERNAL VCXO PLL COMPONENTS

In general, the loop damping factor should be 0.7 or greater to

ensure output stability. A higher damping factor will create less

peaking in the passband. A higher damping factor may also

increase lock time and output clock jitter when there is excess

digital noise in the system application, due to the reduced ability

of the PLL to respond to and therefore compensate for phase

noise ingress.

27/30

28/31

LF1

LF0

ISET

SET

The external crystal devices and loop filter components should

be kept close to the device. Loop filter and crystal PCB

connection traces should be kept short and well separated from

each other and from other signal traces. Other signal traces

shouldnot run underneath the device, the loop filter or crystal

components.

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