PIC16F684-ESLASHST datasheet(66/164 Pages) MICROCHIP

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PIC16F684

DS41202C-page 64

Preliminary

 2004 Microchip Technology Inc.

9.1.4

CONVERSION CLOCK

The A/D conversion cycle requires 11 TAD. The source

of the conversion clock is software selectable via the

ADCS bits (ADCON1<6:4>). There are seven possible

clock options:

•FOSC/2

•FOSC/4

•FOSC/8

•FOSC/16

•FOSC/32

•FOSC/64

•FRC (dedicated internal oscillator)

For correct conversion, the A/D conversion clock

(1/TAD) must be selected to ensure a minimum TAD of

1.6

µs. Table 9-1 shows a few TAD calculations for

selected frequencies.

TABLE 9-1:

TAD VS. DEVICE OPERATING FREQUENCIES

9.1.5

STARTING A CONVERSION

The A/D conversion is initiated by setting the

GO/DONE bit (ADCON0<1>). When the conversion is

complete, the A/D module:

• Clears the GO/DONE bit

• Sets the ADIF flag (PIR1<6>)

• Generates an interrupt (if enabled)

If the conversion must be aborted, the GO/DONE bit

can be cleared in software. The ADRESH:ADRESL

registers will not be updated with the partially complete

A/D

conversion

sample.

Instead,

the

ADRESH:ADRESL registers will retain the value of the

previous conversion. After an aborted conversion, a

2TAD delay is required before another acquisition can

be initiated. Following the delay, an input acquisition is

automatically started on the selected channel.

FIGURE 9-2:

A/D CONVERSION TAD CYCLES

A/D Clock Source (TAD)

Device Frequency

Operation

ADCS2:ADCS0

20 MHz

5 MHz

4 MHz

1.25 MHz

2 TOSC

000

100 ns(2)

400 ns(2)

500 ns(2)

1.6

µs

4 TOSC

100

200 ns(2)

800 ns(2)

1.0

µs(2)

3.2

µs

8 TOSC

001

400 ns(2)

1.6

µs2.0 µs6.4 µs

16 TOSC

101

800 ns(2)

3.2

µs4.0 µs

12.8

µs(3)

32 TOSC

010

1.6

µs6.4 µs

8.0

µs(3)

25.6

µs(3)

64 TOSC

110

3.2

µs

12.8

µs(3)

16.0

µs(3)

51.2

µs(3)

A/D RC

x11

2-6

µs(1,4)

2-6

µs(1,4)

2-6

µs(1,4)

2-6

µs(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1:

The A/D RC source has a typical TAD time of 4

µs for VDD > 3.0V.

These values violate the minimum required TAD time.

For faster conversion times, the selection of another clock source is recommended.

When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the

conversion will be performed during Sleep.

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the A/D.

TAD1

TAD2

TAD3

TAD4

TAD5

TAD6

TAD7

TAD8

TAD9

Set GO bit

Holding Capacitor is Disconnected from Analog Input (typically 100 ns)

TAD10 TAD11

TCY to TAD

Conversion Starts

ADRESH and ADRESL registers are Loaded,

GO bit is Cleared,

ADIF bit is Set,

Holding Capacitor is Connected to Analog Input

PIC16F684-E/ST Datasheet(PDF) 66 Page - Microchip Technology

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